Overlapping Capacitive Elements in OLED Sub Pixels

The patent transitions from a two-dimensional planar arrangement of capacitive elements to a three-dimensional stacked configuration. Capacitive elements are arranged in multiple layers (first, second, and third layers) that overlap vertically, allowing the capacitance to be increased by utilizing the vertical dimension rather than expanding horizontally. This multi-layer stacking enables sufficient capacitance while maintaining a compact footprint that accommodates patterning requirements for distinguishing adjacent sub pixels.

The patent implements a nested arrangement where capacitive elements in different layers are vertically stacked and overlap with each other. The first, second, and third capacitive elements are positioned such that they occupy overlapping vertical spaces, creating a nested configuration. This allows the effective capacitance area to be multiplied while the horizontal footprint remains constrained within the sub pixel boundaries, effectively nesting multiple capacitive functions within a limited planar space.

The patent resolves the patterning-capacitance trade-off by moving the capacitance multiplication strategy from the horizontal plane to the vertical dimension. Instead of requiring large lateral areas that would complicate patterning, the design stacks capacitive elements in multiple vertical layers. Each layer can be patterned with standard dimensions, while the overall capacitance is enhanced by the cumulative effect of multiple layers, thus maintaining manufacturing feasibility while achieving sufficient capacitance.