Overlapping Capacitor Layout for Higher-Resolution Display Pixels

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Solution Overview

Problem

Existing display apparatuses face challenges in optimizing the layout and arrangement of capacitors and connection lines, which can affect the resolution and efficiency of pixel arrangements, particularly in flexible and bendable displays.

Innovation Solution

The display apparatus incorporates a design where capacitors overlap in the depth direction, with transistors and electrodes arranged on different layers, allowing for a multi-layered structure of connection lines that increase pixel density and improve resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If capacitors and connection lines are arranged in a conventional single-layer layout, then the layout is simple and easy to manufacture, but the pixel density and resolution are limited

Engineering Contradiction:
Improvepixel densityVSAvoidlayout complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent transitions from a conventional two-dimensional planar layout to a three-dimensional multi-layer structure. Capacitors are stacked vertically with their plates positioned on different layers (e.g., first capacitor plate on a first layer, second capacitor plate on a second layer), and connection lines are routed through multiple layers to connect components. This vertical stacking enables higher pixel density and resolution while maintaining manufacturability through systematic layer-based organization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If connection lines are arranged on the same layer, then the layout is simple, but the resistance and signal loss increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidconnection line arrangement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Connection lines are distributed across multiple layers rather than confined to a single layer. The first connection line is positioned on a first layer, the second connection line on a second layer, and the third connection line on a third layer. This multi-layer arrangement reduces the total length of connection paths, minimizes resistance, and improves signal integrity while maintaining systematic routing through each layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If capacitors are placed adjacent to each other in a planar arrangement, then the layout is simple, but the space efficiency and pixel density are reduced

Engineering Contradiction:
Improvepixel densityVSAvoidcapacitor arrangement
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Capacitors are stacked vertically in a three-dimensional arrangement rather than placed side-by-side in a planar configuration. The first capacitor and second capacitor are positioned on different layers with their plates alternating (first capacitor plate on first layer, second capacitor plate on second layer). This vertical stacking maximizes space utilization, increases pixel density, and maintains systematic capacitor placement through layer-based organization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250338742A1Display apparatus including overlapping elements
Publication Date: 2025.10.30 SAMSUNG DISPLAY CO LTD
  • US20250338742A1 patent drawing
  • US20250338742A1 patent drawing
  • US20250338742A1 patent drawing

AI summary

A display apparatus includes a first transistor including a first semiconductor layer and a first electrode that at least partially overlaps the first semiconductor layer. A first capacitor includes the first electrode and a second electrode that at least partially overlaps the first electrode. A second capacitor includes the second electrode and a third electrode that at least partially overlaps the second electrode. A first data line is configured to transfer a data voltage therethrough. First and second scan lines are configured to transfer first and second scan signals therethrough, respectively. A second transistor connects the first data line to the second electrode in response to the first scan signal. A third transistor connects the first electrode to a drain of the first transistor in response to the second scan signal.