Overlapping Capacitor Pixel Circuits for High-Density Flexible Displays
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Solution Overview
Problem
Existing display apparatuses face challenges in optimizing the layout and connectivity of capacitors and connection lines, which can affect the resolution and efficiency of pixel arrangements, particularly in flexible and bendable displays.
Innovation Solution
The display apparatus incorporates a design where capacitors overlap in the depth direction, with transistors and electrodes arranged on different layers, allowing for increased pixel density and improved connectivity through multi-layered connection lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitors and connection lines are arranged in a conventional planar layout, then the layout is simple to manufacture, but the pixel density and resolution are limited
Solution Approach 1:
The patent applies dimensionality change by arranging capacitors and connection lines in the depth direction (stacked configuration) rather than only in the plane. Specifically, the first capacitor is positioned at a first depth position while the second capacitor is positioned at a second depth position, allowing multiple capacitors to occupy overlapping planar spaces at different depths. This vertical stacking enables higher pixel density without proportionally increasing planar area usage, effectively resolving the contradiction between pixel density and layout complexity.
2Manufacturing precision
If multiple capacitors are arranged in the depth direction, then pixel density and resolution are enhanced, but the device structure becomes more complex
Solution Approach 1:
The patent merges multiple capacitor structures into a compact stacked arrangement where the first and second capacitors share overlapping planar footprints at different depth positions. This merging approach allows the capacitors to be integrated within a confined vertical space, enhancing resolution while controlling overall device complexity through shared structural elements and compact positioning.
3Productivity
If connection lines are arranged on different layers, then connectivity and signal transfer efficiency are improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements connection lines on different depth layers to improve signal transfer efficiency. The first connection line is positioned at a first depth position connecting to the first capacitor, while the second connection line is positioned at a second depth position connecting to the second capacitor. This vertical separation in the depth direction allows simultaneous signal routing to multiple capacitors without planar interference, enhancing productivity and signal efficiency while managing manufacturing complexity through structured multi-layer fabrication.
Data Source
AI summary
A display apparatus includes a first transistor including a first semiconductor layer and a first electrode that at least partially overlaps the first semiconductor layer. A first capacitor includes the first electrode and a second electrode that at least partially overlaps the first electrode. A second capacitor includes the second electrode and a third electrode that at least partially overlaps the second electrode. A first data line is configured to transfer a data voltage therethrough. First and second scan lines are configured to transfer first and second scan signals therethrough, respectively. A second transistor connects the first data line to the second electrode in response to the first scan signal. A third transistor connects the first electrode to a drain of the first transistor in response to the second scan signal.