Overlapping Segmented DAC for Monotonic High-Resolution Conversion
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Solution Overview
Problem
Conventional segmented DACs face non-monotonicity issues due to the requirement for precise matching between the upper and lower segment DACs, leading to potential system oscillations and instability in feedback loops, especially when the LSB of the H-DAC does not exactly equal the full range of the L-DAC, making them impractical for high-resolution applications.
Innovation Solution
An overlapping segmented DAC architecture is introduced, where a moving segment decoder converts the M-bit input into S-bit and R-bit inputs for the HR-DAC and LR-DAC, respectively, allowing the LR-DAC to operate beyond its conventional toggle point and dynamically adjust the operating range to maintain monotonicity, reducing the need for precise matching between the two segments and preventing oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional segmented DAC architecture is used, then device complexity is reduced, but manufacturing precision requirement increases due to strict matching requirements between H-DAC and L-DAC segments
Solution Approach 1:
The patent divides the M-bit DAC into multiple segments (H-DAC and L-DAC) with different bit resolutions, where the L-DAC has at least two more bits than the H-DAC. This segmentation allows each segment to operate within its optimized range, reducing the overall matching precision requirements while maintaining high resolution through the combined output of multiple segments
Solution Approach 2:
The patent introduces a novel inter-segment transition point detection mechanism that operates in the boundary region between H-DAC and L-DAC ranges. By detecting transition points and dynamically adjusting segment activation, the system resolves the matching precision issue by adding a control dimension that manages the transition between segments, eliminating the need for strict matching at segment boundaries
2Speed
If conventional segmented DAC is used, then conversion speed is improved, but reliability deteriorates due to non-monotonicity and system oscillation in feedback loops
Solution Approach 1:
The patent implements a feedback mechanism that detects inter-segment transition points and uses this information to dynamically adjust the operation of H-DAC and L-DAC segments. This feedback ensures monotonicity by preventing the non-monotonic behavior that causes oscillations in conventional segmented DACs, while maintaining fast conversion speed through efficient segment management
Solution Approach 2:
The patent makes the DAC operation dynamic by continuously monitoring transition points and adjusting segment activation in real-time. This dynamic adjustment ensures monotonicity across the entire input range, preventing system oscillations while maintaining the fast conversion speed advantage of segmented architecture
3Measurement precision
If higher bit resolution is implemented, then measurement precision is improved, but device complexity increases due to more current sources required
Solution Approach 1:
The patent achieves high bit resolution by segmenting the DAC into multiple lower-resolution segments (H-DAC and L-DAC) rather than using a single high-resolution segment. This reduces the number of current sources required compared to a conventional single-segment approach, as each segment uses fewer current sources while the combined output achieves the desired high resolution
Data Source
AI summary
A controller receives an M-bit input and generates, in response, an S-bit upper range binary data feeding S-bit high range DAC and an R-bit lower range data feeding an R-bit low range DAC. The controller detects transition points in the M-bit input and in response, adds a transition data to the S-bit data equal to at least one least significant bit of the S-bit data and subtracts a value from the R-bit data equal to the transition data. The transition points and the transition data are detected and added at points avoiding such transitions at a full scale value of the R-bit data.