Overlapping-Die Power Module Layout for High Power Density
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high power density and current ratings while maintaining a compact footprint, and in minimizing thermal mismatch.
Innovation Solution
The semiconductor package design includes a substrate with multiple dies, a lead frame overlapping the substrate, and tie bars for support, allowing for overlapping dies and a lead frame that overlaps the substrate, thereby increasing substrate size without increasing the package footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the substrate size is increased to achieve higher power density and current ratings, then the power density and current ratings are improved, but the package footprint increases
Solution Approach 1:
The lead frame is nested over the substrate, with the lead frame extending beyond the substrate boundaries. This nesting arrangement allows the electrical connections and external interfaces to be positioned on the lead frame while the power-dissipating substrate maintains its compact size, thereby achieving high power density without increasing the overall package footprint.
Solution Approach 2:
The design transitions from a planar co-location of substrate and lead frame to a three-dimensional overlapping configuration. The lead frame is positioned in a layer above the substrate, utilizing the vertical dimension to accommodate both components within a compact footprint while maintaining the substrate's compact size for high power density.
2Reliability
If the substrate size is increased to achieve higher current ratings, then the current ratings are improved, but the package footprint increases
Solution Approach 1:
The lead frame is nested over the substrate, allowing the substrate to maintain its compact size for high current ratings while the lead frame provides the necessary electrical pathways and external connections without increasing the package footprint.
Solution Approach 2:
The lead frame is positioned in a layer above the substrate, utilizing the vertical dimension to accommodate high-current electrical pathways without expanding the horizontal footprint, thereby maintaining compact package size while achieving higher current ratings.
3Temperature
If thermal mismatch is minimized through material selection, then thermal performance is improved, but device complexity increases
Solution Approach 1:
The substrate is constructed with a layered structure comprising a first substrate layer and a second substrate layer, each with different thermal expansion coefficients. This parameter change in the substrate's thermal properties allows for minimized thermal mismatch without requiring complex external thermal management structures, thereby reducing device complexity.
Data Source
AI summary
Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.