Overlapping Mapping Pages in Flash Memory Controllers

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Solution Overview

Problem

Flash memory systems face performance degradation due to the need to erase blocks before writing, which is inefficient compared to reading or writing operations, and the Flash Translation Layer's logical-to-physical address mapping process can lead to inefficiencies in managing memory operations.

Innovation Solution

The implementation of a memory system that overlaps ranges of mapping pages by duplicating mapping tables between adjacent pages, allowing for efficient loading of mapping tables based on the starting address of a read command, thereby reducing the need to access multiple pages and improving read performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If mapping tables are stored sequentially in non-volatile memory pages without overlap, then memory space is efficiently utilized, but read operations may require accessing multiple pages causing performance degradation

Engineering Contradiction:
Improveread speedVSAvoidmapping table management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by duplicating mapping tables at the boundary of memory pages before read operations occur. Specifically, the last N mapping tables of a first mapping page are copied to the first N positions of a second mapping page, creating an overlapped range. This pre-positioning ensures that when a read command's starting address falls within the overlapped range, the required mapping tables are already available in the current page without requiring access to the next page, thus improving read speed while managing complexity through structured duplication.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the Flash Translation Layer uses a logical-to-physical address mapping table to manage operations, then address translation is achieved, but the system suffers from performance degradation due to erase-before-write architecture and inefficient memory management

Engineering Contradiction:
Improvememory operation efficiencyVSAvoidtime for erase and write operations
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies segmentation by dividing the mapping table storage into multiple mapping pages, each capable of storing a specific number of mapping tables. The mapping tables are organized in sequential order across these pages, with the ability to identify and access specific ranges based on logical address starting positions. This segmentation allows the system to manage large numbers of mapping tables efficiently and enables selective loading of only the required mapping tables for a given read operation, improving memory operation efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by pre-duplicating mapping tables at page boundaries. The last N mapping tables of a first mapping page are copied to the first N positions of a second mapping page before any read operations occur. This creates an overlapped range that ensures mapping tables are readily available when needed, eliminating the need for time-consuming page switches during read operations and reducing the time for memory operations.

Inventive Principle:
Principle #10Preliminary action

3Speed

If mapping tables are duplicated at page boundaries to prevent over NVM page boundary problems, then read performance is improved, but additional memory space is consumed for the duplicated tables

Engineering Contradiction:
Improvereading speedVSAvoidmemory space
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent applies partial action by duplicating only a specific number N of mapping tables at the boundary between mapping pages, rather than duplicating all mapping tables or using full overlap. The value of N is chosen based on the maximum number of mapping tables that may be accessed in a single read operation. This partial duplication provides sufficient performance improvement for typical read operations while minimizing the additional memory space consumption compared to more extensive duplication strategies.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10956318B2Overlapping ranges of pages in memory systems
Publication Date: 2021.03.23 MACRONIX INTERNATIONAL CO LTD
  • US10956318B2 patent drawing
  • US10956318B2 patent drawing
  • US10956318B2 patent drawing

AI summary

Systems, methods, and apparatus including computer-readable mediums for managing memories by overlapping ranges of pages in nonvolatile memory systems are provided. An example memory system includes a memory controller coupled to a memory and configured to: determine a range of logical addresses associated with a command, search particular mapping tables including the range of logical addresses in mapping pages in the memory, determine whether a starting address of the range of logical addresses is in an overlapped range of first and second sequential mapping pages, the overlapped range including logical addresses of one or more mapping tables duplicated in the first and second mapping pages, determine which of the first and second mapping pages from which the particular mapping tables to be loaded based on a result of determining whether the starting address is in the overlapped range, and load the particular mapping tables from the determined mapping page.