Overlapping Magnetic Tunnel Junctions for Reduced Pitch Memory Density
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Solution Overview
Problem
Conventional memory device fabrication techniques are limited by lithographic processes, resulting in large pitches between magnetic tunnel junction (MTJ) memory cells, which restricts memory cell density and storage capacity.
Innovation Solution
The implementation of a magnetic tunnel junction memory device with pMTJs in different levels, where the location of one pMTJ is coordinated with respect to another based on a reference pitch, allowing for overlap or spacing that compensates for lithographic limitations, thereby reducing the pitch between memory cells and increasing storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to fabricate MTJ memory cells, then the manufacturing process is simple and well-established, but the pitch between memory cells is large (approximately 90 nm), limiting memory cell density
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of MTJ memory cells to a three-dimensional multi-level structure. By stacking MTJ cells across multiple levels (e.g., first level and second level), the pitch between cells is reduced while maintaining manufacturability through coordinated lithographic processes across different layers. This vertical dimensionality change enables higher density without requiring smaller lateral features that would exceed lithographic capabilities.
2Reliability
If the MTJ size is trimmed down to smaller dimensions (e.g., 20 or 30 nm), then current and voltage characteristics improve, but the pitch remains limited by lithographic placement (approximately 90 nm), so density does not increase
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to reduce pitch. While MTJ cells at each level maintain their functional size (20-30 nm) for optimal electrical characteristics, the pitch is reduced by stacking levels vertically rather than by further reducing lateral dimensions. This allows the pitch to scale below the lithographic limit through multi-level coordination, where the vertical separation between levels provides the density improvement without compromising the electrical performance of individual cells.
3Quantity of substance
If multi-level overlapping MTJ structures are implemented to reduce pitch, then memory cell density and storage capacity increase, but the device structure and fabrication process become more complex
Solution Approach 1:
The patent applies segmentation by dividing the memory device into multiple discrete levels, each containing MTJ cells. This segmentation allows independent fabrication and optimization of each level while achieving overall high density through vertical stacking. The coordinated lithographic processes treat each level as a separate but related unit, enabling complex multi-level structures to be built from simpler, repeatable level units.
Solution Approach 2:
The patent reduces pitch and increases density by exploiting the vertical dimension through multi-level stacking. Rather than compressing cells laterally in two dimensions, the structure extends into the third dimension, allowing cells to be arranged in multiple levels where vertical pitch determines the overall density. This approach manages complexity by using the unused vertical space that is typically wasted in planar devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a reduced pitch between memory cells, enhancing memory cell density and information storage capacity per device area, beyond the limitations of traditional lithography.
Implementation Method 1
Magnetic memory devices typically store information by adjusting and holding magnetic fields within components of the device
Implementation Method 2
A MTJ typically includes ferromagnetic portions separated by a non-magnetic material. The magnetic orientation or spin of a ferromagnetic portion can be altered
Implementation Method 3
The magnetic orientation or spin of a ferromagnetic portion can be altered and results in a change to the electrical resistive characteristics of the device
Data Source
AI summary
Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a semiconductor device comprises: a first pillar magnetic tunnel junction (pMTJ) memory cell that comprises a first pMTJ located in a first level in the semiconductor device; and a second pillar magnetic tunnel junction (pMTJ) memory cell that comprises a second pMTJ located in a second level in the semiconductor device, wherein the second pMTJ location with respect to the first pMTJ is coordinated to comply with a reference pitch for the memory cell. A reference pitch is associated a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The first switch and second switch can be transistors. The reference pitch coordination facilitates reduced pitch between memory cells and increased information storage capacity of bits per memory device area.