Overlapping NAND Die Stacks for Higher Density Wirebonding
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Solution Overview
Problem
Existing semiconductor die stacking methods face limitations in increasing capacity and performance due to overhang issues and increased manufacturing complexity, particularly in shingled stacking arrangements.
Innovation Solution
The implementation of overlapping die stacks with asymmetric heights, where one stack partially overlaps another, allowing for a single uninterrupted wirebonding operation and reducing surface area occupation, thereby enabling higher die density and simplified manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple dies are stacked on top of each other to increase capacity, then the device capacity and performance are improved, but the manufacturing complexity and overhang issues increase
Solution Approach 1:
The patent employs asymmetric die stacking where dies of different sizes are stacked in an asymmetric arrangement. Larger dies are positioned at lower levels while smaller dies are positioned at upper levels, creating an asymmetric profile that eliminates overhang issues. This asymmetric configuration allows multiple dies to be stacked without requiring complex support structures, thereby increasing device capacity while maintaining manufacturing simplicity.
Solution Approach 2:
The patent transitions from traditional planar die arrangements to vertical three-dimensional stacking. By arranging dies in multiple vertical layers with asymmetric positioning, the design utilizes the vertical dimension to increase capacity without expanding the lateral footprint. This dimensional change allows more dies to be packed into a smaller surface area while avoiding overhang problems through careful vertical positioning.
2Area of stationary object
If shingled stacking arrangement is used to increase die density, then the surface area occupation is reduced, but the overhang issues and manufacturing complexity increase
Solution Approach 1:
The patent implements asymmetric shingled stacking where dies are arranged in overlapping vertical stacks with varying heights. Each stack contains dies of different sizes positioned asymmetrically, with larger dies at the bottom and smaller dies at the top. This asymmetric arrangement reduces the lateral surface area required while eliminating the overhang issues that plague traditional shingled stacking, thereby maintaining manufacturing ease.
Solution Approach 2:
The patent applies a nested doll principle by positioning smaller dies within the horizontal footprint of larger dies in vertical stacks. This nested arrangement allows multiple dies to occupy overlapping horizontal spaces at different vertical levels, significantly reducing the total surface area required while maintaining structural integrity and avoiding overhang problems through proper vertical nesting.
Data Source
AI summary
A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.