Overlapping N-wells for Voltage Level Shifter Cell Area Reduction
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Solution Overview
Problem
As semiconductor devices integrate more components, there is a need for efficient voltage level shifting between different power domains to reduce power consumption and increase performance, while existing solutions often occupy significant area due to parallel arrangement of N-wells for different power voltages.
Innovation Solution
A voltage level shifter cell design that includes multiple N-wells sharing power voltages, with overlapping N-wells in a Y-axis direction, allowing for parallel arrangement of identical conductivity wells, reducing the overall area occupied by the voltage level shifter cell and integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple N-wells are arranged in parallel for different power voltages, then voltage level shifting between power domains is enabled, but the occupied area increases significantly
Solution Approach 1:
The patent transitions from a two-dimensional parallel arrangement of N-wells to a three-dimensional overlapping configuration. Specifically, first and second N-wells of the same conductivity type are arranged to overlap each other in a vertical dimension, allowing multiple N-wells to share the same planar footprint while maintaining electrical isolation through vertical stacking. This dimensional transition enables voltage level shifting between multiple power domains without proportionally increasing the cell area.
Solution Approach 2:
The patent implements a nested configuration where N-wells of the same conductivity type are positioned within overlapping regions. The first N-well and second N-well are arranged such that one is nested within the overlapping area of the other, allowing multiple wells to coexist in a compact footprint. This nesting approach enables the circuit to accommodate multiple power voltage domains while minimizing the overall cell area occupied by the voltage level shifter.
2Productivity
If more components are integrated in semiconductor devices, then performance and functionality are improved, but power consumption increases
Solution Approach 1:
The patent divides the semiconductor device into multiple power voltage domains, each operating at different voltage levels. By segmenting the device into first and second power voltage domains with respective first and second N-wells, the system can selectively activate components in specific voltage domains based on performance requirements. This segmentation allows high-performance operations in elevated voltage domains while maintaining low-power operation in standard voltage domains, thereby managing overall power consumption.
Solution Approach 2:
The patent applies different voltage levels to different local regions (power domains) of the semiconductor device based on specific performance requirements. The first power voltage and second power voltage are applied to different N-well regions, enabling local optimization where high-performance components operate at higher voltages while other components operate at standard voltages. This local quality approach ensures that power consumption is optimized for each functional block rather than uniformly across the entire device.
3Area of stationary object
If N-wells of the same conductivity type are arranged to overlap, then area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes for first and second N-wells of the same conductivity type by arranging them to overlap in the vertical dimension. This overlapping configuration allows both N-wells to be formed using the same well formation process step, eliminating the need for separate, complex fabrication sequences. The merged approach reduces manufacturing complexity while achieving compact area utilization through vertical stacking of the N-wells.
Data Source
AI summary
A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.