Overlapping Semiconductor Die Coplanar Vertical Interconnect
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Solution Overview
Problem
The existing manufacturing processes for semiconductor devices are costly and complex, particularly in achieving vertical integration of semiconductor packages using conductive through silicon vias (TSV) and through hole vias (THV), which hinders efficient production in competitive markets like memory and application-specific integrated circuits (ASIC).
Innovation Solution
A method for forming overlapping semiconductor die with a coplanar vertical interconnect structure, where a first interconnect structure is formed over a first semiconductor die, and a second interconnect structure is created with a height equal to or greater than the first, allowing the second semiconductor die to overlap, enabling planarization and efficient stacking with reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive through silicon vias (TSV) and through hole vias (THV) are used for vertical integration, then electrical interconnection between stacked packages is achieved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent divides the vertical interconnect structure into separate segments: a first interconnect structure formed over the first semiconductor die, and a second interconnect structure formed over the second semiconductor die. These segmented structures are then combined to achieve the full vertical interconnection function, simplifying the manufacturing process compared to traditional monolithic TSV/THV approaches.
Solution Approach 2:
The patent transitions from planar interconnect structures to three-dimensional coplanar vertical interconnect structures. By forming interconnect structures that extend vertically while maintaining coplanar surfaces, the patent achieves electrical interconnection in the vertical dimension without requiring complex through-silicon via processes.
2Reliability
If traditional TSV/THV processes are used, then vertical integration is achieved, but package thickness and footprint increase
Solution Approach 1:
The patent implements overlapping semiconductor dies where the second semiconductor die is positioned over the first interconnect structure, creating a nested arrangement. This nesting allows vertical integration while minimizing the overall package thickness and footprint, as the dies share overlapping areas rather than requiring separate lateral space.
Solution Approach 2:
The patent achieves vertical integration by forming coplanar surfaces at different heights (first coplanar surface over the first die, second coplanar surface over the second die). This dimensional approach allows stacked packages to be integrated vertically without increasing lateral footprint, resulting in thinner overall packages.
3Reliability
If conventional manufacturing processes are used, then semiconductor devices are produced, but production efficiency is reduced and costs increase
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming the first interconnect structure over the first die, forming the second interconnect structure over the second die, and then combining them. This segmentation allows for parallel processing and simplifies each individual step, improving overall production efficiency and reducing manufacturing costs.
Solution Approach 2:
The patent performs preliminary actions by forming the first and second interconnect structures on separate dies before final assembly. This preliminary formation of interconnect structures allows for independent optimization and manufacturing of each die, improving production efficiency and yield while reducing the complexity of the final assembly process.
Data Source
AI summary
A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.