Overlapping Semiconductor Lead Frame Islands for Compact Stacking
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Solution Overview
Problem
The challenge is to miniaturize semiconductor devices without increasing the package thickness, particularly when stacking child chips on parent chips, as the existing technology results in increased thickness due to the positioning of thin metal wires connecting the chips.
Innovation Solution
The solution involves a semiconductor device configuration where a first island with a semiconductor chip on its upper surface and a second island with a semiconductor chip on its rear surface are partially overlapping, with leads on both islands sealed by an insulating resin, allowing for reduced planar area occupation and maintaining electrical connectivity without additional thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a child chip is stacked on a parent chip using thin metal wires for electrical connection, then electrical connectivity between chips is achieved, but the package thickness increases
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional lead frame interconnection. Leads extend vertically between stacked chips, utilizing the thickness dimension for electrical connection rather than requiring wires to bridge gaps horizontally. This dimensional change enables compact stacking without increasing overall package thickness.
Solution Approach 2:
The patent implements nested positioning where the second island is positioned within the planar footprint of the first island. This nesting arrangement allows chips to be stacked vertically with leads passing through overlapping regions, maximizing space utilization and preventing thickness increase from wire connections.
2Adaptability or versatility
If multiple chips are stacked on an island, then device functionality is enhanced, but the planar area occupied increases
Solution Approach 1:
The patent moves from two-dimensional planar arrangement to three-dimensional vertical stacking. Multiple chips are arranged in the thickness direction rather than spreading out on the planar surface, enabling enhanced functionality within a compact footprint by utilizing the vertical dimension for chip placement.
Solution Approach 2:
The patent employs nested positioning where the second island is positioned within the planar boundaries of the first island. This allows multiple chips to occupy overlapping planar areas at different vertical levels, reducing the overall planar footprint while accommodating multiple functional chips.
Data Source
AI summary
By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.