Overlapping Test Pad and External Connector Layout for Scaled Electronics
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Solution Overview
Problem
The scaling down of semiconductor structures leads to issues affecting electrical characteristics, quality, cost, and yield, particularly in the context of semiconductor devices.
Innovation Solution
The implementation of a conductive structure with a test pad and an external connector on a substrate, where the external connector is electrically connected and exposed for external connection, and a vertical projection of the connector overlaps the test pad, allowing for efficient testing and reduced vertical space occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor structures are scaled down to meet application requirements, then device size is reduced, but electrical characteristics and manufacturing quality deteriorate
Solution Approach 1:
The patent transitions from planar 2D conductor layouts to three-dimensional vertical conductor structures. Conductors extend through multiple layers and interfaces in the vertical dimension, enabling compact device footprints while maintaining adequate current carrying capacity and electrical performance through the third dimension.
Solution Approach 2:
The patent implements nested conductor configurations where conductors are positioned within and between device layers. Conductors are embedded in dielectric layers, surrounded by barrier layers, and integrated with contact regions, creating a nested multi-layer structure that optimizes electrical connectivity in scaled devices.
2Volume of moving object
If semiconductor structures are scaled down, then device size is reduced, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent employs universal conductor formation processes that can be applied across multiple device types and fabrication nodes. The same sequential deposition and patterning techniques used for smaller features can also form larger conductors, allowing manufacturers to use identical tooling and processes for a range of conductor sizes without requiring separate manufacturing lines.
Solution Approach 2:
The patent utilizes parameter changes in deposition thickness and pattern dimensions to scale conductor sizes. By adjusting deposition parameters and lithographic dimensions, the same fundamental process sequence can produce conductors of varying sizes, from nanoscale to larger dimensions, simplifying manufacturing across different device generations.
3Ease of manufacture
If conventional conductor formation processes are used, then manufacturing simplicity is maintained, but conductor size control precision deteriorates
Solution Approach 1:
The patent performs preliminary barrier layer deposition and adhesion layer formation before conductor material deposition. These preliminary layers are deposited with controlled thicknesses that pre-establish the conductor's final dimensions and properties. The barrier layer thickness, deposited first, defines the minimum conductor size and ensures uniform conductor formation across the substrate.
Solution Approach 2:
The patent replaces mechanical patterning and cutting methods with vapor-phase deposition and self-limiting thin film formation. Atomic layer deposition and chemical vapor deposition processes use chemical reactions rather than mechanical removal to define conductor boundaries and thickness, achieving nanoscale precision without mechanical tool wear or alignment errors.
Data Source
AI summary
An electronic device, an electronic structure and a manufacturing method are provided. The electronic device includes a substrate, a conductive structure and at least one external connector. The conductive structure is formed on the substrate and includes a test pad configured to be contacted by a probe during a testing process. The external connector is electrically connected to the conductive structure and is exposed from a surface of the electronic device for an external electrical connection. A vertical projection of the at least one external connector overlaps a vertical projection of the test pad.