Overlapping Underfill Package Structure for Dense Die Integration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The semiconductor industry faces challenges in achieving high integration density and small footprint packaging due to limitations in current packaging techniques, particularly in the stacking and integration of semiconductor dies, which affects the efficiency and functionality of electronic devices.

Innovation Solution

A method for forming a package structure involves using a carrier substrate with a release layer, redistribution structures, and core substrates, where redistribution layers with conductive features are formed on the carrier substrate, and core substrates are bonded using conductive connectors, followed by encapsulation and singulation to create a high-density package configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional packaging techniques are used for semiconductor dies, then the packaging process is simpler, but the integration density and footprint reduction are limited

Engineering Contradiction:
Improveintegration densityVSAvoidpackaging structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The packaging structure is divided into multiple functional layers including carrier substrate, release layer, redistribution structures, core substrates, and encapsulant. This segmentation allows each layer to perform its specific function independently, enabling high integration density while maintaining manageable complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a nested structure where core substrates are bonded to the carrier substrate, which is then encapsulated within a larger package structure. This nesting approach maximizes the use of vertical space, achieving high integration density by stacking functional elements rather than spreading them out laterally

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of moving object

If semiconductor dies are stacked to reduce footprint, then the device size is reduced, but the manufacturing and alignment precision requirements increase

Engineering Contradiction:
Improvepackage footprintVSAvoiddie stacking alignment
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The carrier substrate serves as an intermediary platform that facilitates the bonding of multiple core substrates. This intermediary structure provides a stable base with controlled thermal and mechanical properties, enabling precise alignment and bonding of stacked dies while reducing the overall footprint of the package

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent utilizes controlled thermal parameters during the bonding process to achieve precise alignment and bonding of stacked dies. By carefully controlling temperature profiles during reflow or eutectic bonding, the system achieves high precision die stacking while maintaining a compact package footprint

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If more redistribution layers and conductive features are added, then the integration functionality is enhanced, but the manufacturing process complexity increases

Engineering Contradiction:
Improveintegration functionalityVSAvoidmanufacturing process simplicity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The redistribution structures are designed to perform multiple functions simultaneously: electrical interconnection between dies, thermal management pathways, and mechanical support. This multi-functionality enhances integration capabilities without proportionally increasing manufacturing complexity, as a single structural element serves multiple purposes

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240395783A1Package structure and method of forming thereof
Publication Date: 2024.11.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240395783A1 patent drawing
  • US20240395783A1 patent drawing
  • US20240395783A1 patent drawing

AI summary

A package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. The first die and a second die are disposed on the package substrate. The first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. The second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.