Overlapping Metal Via Interconnect Layout for Smaller Chip Area

The patent applies vertical stacking of metallization layers to transition from a two-dimensional lateral arrangement of vias to a three-dimensional overlapping configuration. Multiple via layers (first via metallization layer, second via metallization layer, third via metallization layer) are stacked vertically with overlapping footprints, allowing interconnects to occupy the same lateral space at different heights. This dimensional transition reduces the device footprint while maintaining connectivity, directly resolving the contradiction between area reduction and scaling efficiency.

The patent implements nesting by placing vias from different metallization layers within the same lateral footprint. Specifically, the second via metallization layer is positioned to overlap with the first via metallization layer, and the third via metallization layer overlaps with the second, creating a nested vertical structure. This nesting approach allows multiple interconnect paths to share the same lateral space, reducing the overall area while preserving signal routing functionality.

The patent employs preliminary action through the formation of mandrel structures and sacrificial layers before creating the final via holes. The process includes depositing mandrel material, forming mandrels with desired patterns, depositing sacrificial material over mandrels, etching vias through the sacrificial and dielectric layers, and finally removing mandrels. This preliminary structuring establishes precise via locations and dimensions before the overlapping via layers are formed, reducing alignment complexity by pre-defining the geometric relationships between vias in different layers.

The patent segments the via formation process into distinct stages for different via layers. Each via layer (first, second, third via metallization layers) is formed through separate etching and filling operations, allowing independent optimization and control of each layer's geometry and position. This segmentation enables precise alignment between overlapping vias by treating each layer as an independent formation step with its own patterning and etching parameters, thereby managing the complexity of creating multi-layer overlapping structures.