Vertically Overlapping Wordlines for Resistive Memory Density
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Solution Overview
Problem
Resistive memory cells face performance bottlenecks due to high resistance of polysilicon wordlines, which can be mitigated but at the cost of decreased cell density when metal straps are used.
Innovation Solution
Implementing vertical overlapping wordlines in multiple layers above the memory cell array, eliminating the need for strapping structures and thereby increasing device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal straps are used to connect to wordlines, then performance is improved, but cell density decreases
Solution Approach 1:
The patent transitions from planar wordline connections to three-dimensional vertical stacking, with wordlines arranged in multiple layers above the memory cell array. This spatial reconfiguration eliminates the need for lateral metal strap extensions, thereby improving cell density while maintaining electrical connection performance through vertical contact structures.
Solution Approach 2:
The patent implements nested wordline structures where multiple wordline layers are vertically stacked and interconnected through contact structures. Each wordline layer is positioned above the previous one, creating a compact nested arrangement that reduces lateral footprint while maintaining multiple connection points along the gate structure axial length.
2Ease of manufacture
If polysilicon wordlines are used, then manufacturing is simplified, but resistance increases causing performance bottleneck
Solution Approach 1:
The patent employs composite conductor structures combining polysilicon gate materials with metal contact and interconnect structures. The polysilicon maintains ease of manufacture for the gate, while metal contacts and vertical interconnect structures provide low-resistance pathways, creating a composite system that balances manufacturing simplicity with electrical performance.
Solution Approach 2:
The patent introduces metal contact structures as intermediary elements between the polysilicon wordline and the memory cell array. These metal contacts serve as mediators that bridge the high-resistance polysilicon gate with the low-resistance requirements of the memory operation, allowing polysilicon to be used for manufacturing simplicity while metal ensures performance.
Data Source
AI summary
One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.