Overlapping Write Schemes for Cross-Point NVM
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Solution Overview
Problem
Current solid-state storage devices with cross-point non-volatile memory architectures face limitations in executing multiple write operations within a single tile in parallel due to power supply constraints, leading to slower write operation times.
Innovation Solution
The technique involves overlapping and reordering write operations, where a second electrical pulse is applied to a second cell before the first pulse has concluded in a single tile, and prioritizing SET operations over RESET operations to optimize current usage and reduce write time without exceeding the maximum current capacity of the tile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple write operations are executed sequentially in a single tile, then power supply constraints are satisfied, but write operation time increases
Solution Approach 1:
The controller receives multiple write operations and prepares them in advance by identifying which operations can be overlapped. It determines the execution order and timing of electrical pulses before actually applying them, allowing the second write operation to be prepared while the first is still in progress, thus reducing total write time while maintaining power constraints
Solution Approach 2:
The patent implements overlapping write operations where the second electrical pulse is applied before the first pulse has fully concluded. This continuous action allows multiple write operations to proceed simultaneously in different cells within the same tile, maximizing utilization of the power supply capacity and eliminating idle time between operations
2Speed
If write operations are executed in parallel in a single tile, then write speed increases, but power supply capacity is exceeded
Solution Approach 1:
The patent applies different timing strategies to different cells within the same tile based on their specific write operation requirements. By analyzing individual cell characteristics and operation types (SET vs RESET), the controller optimizes the pulse application timing for each cell, allowing parallel operations to proceed at optimal speeds without exceeding the tile's maximum current capacity
Solution Approach 2:
The controller dynamically adjusts the timing and duration of electrical pulses based on real-time conditions. It determines when to apply the second pulse relative to the first pulse completion, optimizing the overlap duration to maximize write speed while ensuring the total current demand remains within the power supply's maximum capacity at any given moment
3Use of energy by moving object
If SET operations are prioritized over RESET operations, then current usage is optimized, but operation ordering complexity increases
Solution Approach 1:
The controller receives multiple write operations and preliminarily sorts them by operation type, prioritizing SET operations over RESET operations in the execution queue. This pre-ordering strategy allows the controller to apply electrical pulses in an optimized sequence that minimizes total current usage, as SET operations can be overlapped more effectively with subsequent operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster execution of write operations by overlapping pulses and reordering commands, thereby reducing overall write time and increasing the number of operations that can be performed within a given time frame without compromising the integrity of the write process.
Implementation Method 1
Memristor technology may store data based on the electrical resistance of respective memristors. Memristors may change between a high-resistance state and a low-resistance state based on an amount and direction of electrical current to which the memristor was most recently exposed.
Data Source
AI summary
A first write operation is received. The first write operation includes a SET operation. The SET operation is configured to place a cell of the non-volatile memory (NVM) device in a relatively low-resistance state. A second write operation is received. A first electrical pulse is applied to a first cell of the NVM device. The first electrical pulse is applied to place the first cell in the relatively low-resistance state. A second electrical pulse is applied to a second cell of the NVM device. The second electrical pulse is applied before the first electrical pulse has concluded. The second cell and the first cell are both within a single tile of the NVM device.