Overlay Alignment Mark Segmentation for IC Fabrication
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Solution Overview
Problem
In the fabrication of integrated circuitry, achieving precise overlay alignment between different layers is challenging due to misalignment issues, which can lead to failed or inoperative circuits, impacting yield and profitability.
Innovation Solution
A method of forming an overlay alignment mark by creating a first series of periodically-horizontally-spaced lower features on a substrate and a second series of upper features directly above, with specific horizontal areas where the upper features cover or do not cover the lower features, allowing for precise alignment determination using metrology equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional overlay alignment marks (e.g., box-in-box constructions) are used to compare alignment, then alignment control is achieved, but misalignment of sufficient degree still results in failed or inoperative finished construction which impacts yield and profit margin
Solution Approach 1:
The overlay alignment mark is segmented into distinct upper and lower feature sets, each formed at different elevation levels. The lower features are formed on the substrate surface while upper features are formed on an elevated surface, allowing independent measurement and comparison of alignment between layers through metrology equipment that can detect the relative positioning of these segmented features.
Solution Approach 2:
The invention transitions from two-dimensional planar alignment marks to three-dimensional elevated features. By forming upper features on an elevated surface above the substrate, the alignment mark system adds a vertical dimension that enables more precise measurement and detection of overlay alignment using optical or other metrology equipment that can resolve the spatial relationship between elevated and substrate-level features.
2Adaptability or versatility
If multiple patterning steps are used to deposit electronic components in layers, then circuit complexity and functionality are improved, but the alignment control between separate patterning steps becomes more challenging
Solution Approach 1:
The lower overlay alignment features are formed preliminarily during the substrate preparation stage, before the upper features are created. This preliminary formation of reference features establishes a stable baseline for subsequent alignment operations, allowing each patterning step to reference the previously formed features and maintain precise alignment across multiple fabrication steps.
Solution Approach 2:
The elevated upper features serve as an intermediary reference structure that mediates the alignment between different patterning steps. By creating measurable features at an elevated level that correspond to lower substrate features, the system provides a intermediary reference that facilitates precise alignment control without requiring direct measurement between all pattern layers.
Data Source
AI summary
A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.