Overlay Error Compensation Using Actual Device Structures
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Solution Overview
Problem
Current overlay compensation methods in semiconductor manufacturing fail to improve overlay accuracy effectively, leading to low product yield due to the reliance on overlay marks that cannot accurately represent the real pattern positions.
Innovation Solution
A method and system that determine overlay errors based on actual device structures of present and previous layers, calculating compensation values to accurately reflect the relative position between these structures, thereby improving overlay accuracy by averaging compensation values across multiple wafers and applying them to subsequent wafer groups within a preset range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If overlay marks are used to determine overlay error, then the measurement process is simple, but the overlay accuracy is insufficient because overlay marks cannot accurately represent real pattern positions
Solution Approach 1:
The patent extracts the measurement target from conventional overlay marks to the actual device structures themselves. By directly measuring the relative positions of present layer and previous layer device structures, the system obtains accurate overlay error data that truly reflects pattern alignment, eliminating the representation error inherent in using separate overlay marks.
Solution Approach 2:
The patent creates a virtual model of the ideal device structure position based on design data, then compares it with the actual measured position of device structures. This copying approach enables precise quantification of overlay error by calculating the deviation between the virtual ideal position and the real measured position.
2Productivity
If overlay compensation is not applied, then the manufacturing process is simple, but the product yield is low due to poor overlay accuracy
Solution Approach 1:
The patent implements a feedback loop where overlay errors are measured from actual device structures, processed through calculation and averaging, then fed back to the batch control system to adjust compensation parameters for subsequent wafer groups. This closed-loop feedback mechanism continuously improves overlay accuracy and thereby increases product yield.
Solution Approach 2:
The patent performs preliminary overlay error measurement and compensation calculation on current wafer groups before processing subsequent wafer groups. By calculating average compensation values in advance and applying them to the next wafer group, the system proactively prevents overlay errors rather than reacting to them after they occur.
Data Source
AI summary
Disclosed are a method and system for overlay error compensation and a storage medium. The method includes that N wafer groups are provided, wherein each wafer group includes M wafers each including a present and previous layer, and N and M are positive integers greater than or equal to 2; for each wafer, a first overlay error is determined according to device structures of the present and previous layers, and a photoetching compensation value is calculated according to the first overlay error; for each wafer group, a first average compensation value is calculated according to photoetching compensation values; a second average compensation value of the N wafer groups is calculated according to first average compensation values; and in response to that the second average compensation value is within a preset range, the second average compensation value is fed to a batch control system to compensate an (N+1)th wafer group.