Overlay Error Compensation Using Run Path Segmentation
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Solution Overview
Problem
Current advanced process control (APC) systems in photolithography only compensate overlay errors between the current layer and the previous layer, neglecting errors between the actual and theoretical exposed patterns, leading to out-of-specification issues and increased process rework rates.
Innovation Solution
An optimization method and system that sets multiple groups of process parameters for each semiconductor layer, considering different run paths and using high-order non-linear mathematical models to correct overlay errors between actual and theoretical patterns, thereby updating process parameters to improve overlay accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current APC systems only compensate overlay errors between current layer and previous layer, then the compensation process is simple, but overlay accuracy deteriorates due to neglecting errors between actual and theoretical exposed patterns
Solution Approach 1:
The system performs preliminary measurement and correction of first-layer within-shot overlay errors before subsequent lithography steps. By measuring the actual exposed pattern of the first layer and calculating correction values in advance, the system prevents error propagation to later layers, thereby improving overall overlay accuracy without requiring complex real-time adjustments during the lithography process
Solution Approach 2:
The system implements a feedback mechanism where overlay errors are measured after first layer exposure, correction values are calculated based on the difference between actual and theoretical patterns, and these corrections are applied to subsequent lithography steps. This closed-loop feedback ensures that errors are continuously identified and compensated, maintaining high overlay accuracy across multiple layers
2Manufacturing precision
If APC systems do not differentiate run paths for different production lots, then the control system is simple, but overlay precision deteriorates due to tool and lot variations
Solution Approach 1:
The system segments the overlay correction process by creating separate correction value sets for different run paths. Each run path (combining specific tool and lot) has its own dedicated correction values stored in a database, allowing the system to select and apply the appropriate correction set based on the actual run path being executed. This segmentation enables precise compensation for tool-specific and lot-specific variations without requiring a single complex universal model
Solution Approach 2:
The system dynamically changes correction parameters based on the identified run path. By storing multiple sets of correction values with different parameters (X-translation, Y-translation, substrate expansion, rotation, magnification, etc.) for different run paths, the system can select and apply the optimal parameter set for each specific tool-lot combination, thereby maintaining high overlay precision across varying conditions
Data Source
AI summary
An optimization method for overlay error compensation is disclosed. The method comprises setting process parameters for each semiconductor layer of a semiconductor device corresponding to a run path formed by different lithographic apparatus which sequentially process target semiconductor layers from a first target layer to a latest target layer; measuring overlay errors between an actual and a theoretical exposed patterns of the first semiconductor layer; selecting a group of process parameters corresponding to the run path from the first target layer to the latest target layer aligned by the current semiconductor layer; after exposing the current semiconductor layer using the selected process parameters, measuring overlay errors between the current semiconductor layer and its target layer; and correcting the selected process parameters according to the overlay errors between the current semiconductor layer and its target layer, and the overlay errors between the actual and theoretical exposed patterns of the first semiconductor layer.