Overlay Error Correction Using Dual Marks

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Solution Overview

Problem

The semiconductor industry faces challenges in accurately measuring overlay errors due to asymmetric shapes of measurement structures, making it difficult to precisely align photoresist patterns and underlying patterns in lithography operations, which requires a new overlay mark and method for precise error measurement.

Innovation Solution

The solution involves using two overlay marks on opposite surfaces of a substrate, where one mark generates a first overlay error indicative of misalignment and the second mark generates a second overlay error to correct the first error, allowing determination of whether the abnormality is caused by misalignment or wafer warpage, thereby preventing inaccurate adjustments to exposure equipment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If traditional overlay marks with asymmetric shapes are used for measurement, then the measurement process can be simplified, but the measurement precision deteriorates due to difficulty in accurately determining overlay errors

Engineering Contradiction:
Improveease of measurementVSAvoidoverlay error measurement precision
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent applies asymmetry principle by designing overlay marks with specific asymmetric geometries (e.g., L-shaped, T-shaped patterns) that when overlaid create distinctive asymmetric combined patterns. This allows the measurement system to easily distinguish between different overlay error conditions while maintaining simple mark structures that are easy to manufacture and measure.

Inventive Principle:
Principle #4Asymmetry

2Productivity

If overlay error measurement is performed without distinguishing warpage effects, then the measurement process is faster, but the reliability deteriorates due to inaccurate adjustment of exposure equipment

Engineering Contradiction:
Improvemeasurement speedVSAvoidequipment adjustment accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the overlay error measurement into two distinct components: (1) misalignment error between photoresist pattern and underlying pattern, and (2) wafer warpage error. By using separate measurement marks positioned at different locations on the wafer, the system can independently measure and distinguish these two error sources, enabling reliable equipment adjustment while maintaining efficient measurement processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate reference marks and measurement structures that serve as mediators between the physical overlay conditions and the measurement system. These intermediate structures (such as reference patterns etched into the substrate) provide stable reference points that help separate the effects of misalignment from warpage, enabling accurate distinction between the two error sources without complicating the overall measurement workflow.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If multiple measurement marks are used to distinguish misalignment from warpage, then the reliability of error determination is improved, but the device complexity increases

Engineering Contradiction:
Improveerror determination accuracyVSAvoidoverlay mark structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs overlay marks with multi-functionality where the same basic mark structure serves multiple purposes: (1) measuring misalignment error, (2) measuring warpage error, and (3) providing reference patterns for both measurements. By making the measurement marks universal and multi-functional, the system achieves reliable error determination without proportionally increasing the overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11796924B2Method for overlay error correction and method for manufacturing a semiconductor device structure with overlay marks
Publication Date: 2023.10.24 NAN YA TECH
  • US11796924B2 patent drawing
  • US11796924B2 patent drawing
  • US11796924B2 patent drawing

AI summary

A method for overlay error correction includes generating a first overlay error based on a first overlay mark, wherein the first overlay error is indicative of a misalignment between a lower pattern and an upper pattern of the first overlay mark. The method also includes generating a second overlay error based on a second overlay mark, in response to an abnormal of the first overlay error is detected. The method further includes determining whether the abnormal of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern depending on the second overlay error.