Overlay Fingerprint Mark Structure Using Pattern Density Maps
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing processes leads to stringent requirements for accuracy in overlay and critical dimension measurements, with existing methods struggling to effectively characterize and minimize errors induced by processes like patterning, etching, and chemical mechanical polishing.
Innovation Solution
The development of a method for designing metrology mark structures using pattern density maps to characterize overlay fingerprints, allowing for the determination of process-induced errors through density modulation of features, enabling precise measurement and extraction of overlay contributions from various semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional overlay measurement methods are used, then measurement capability is maintained, but measurement precision deteriorates due to increasing process complexity and error sources
Solution Approach 1:
The patent segments the overlay measurement problem by introducing separate metrology mark structures for different process stages (patterning, etching, CMP). Each mark structure is optimized for specific process-induced errors, allowing independent characterization and correction of each process step's contribution to total overlay error
Solution Approach 2:
The patent introduces metrology mark structures as intermediary elements between the actual device features and the measurement system. These marks serve as dedicated targets that isolate measurement from device fabrication constraints, enabling precise characterization of process-induced overlay errors without affecting device performance
2Loss of information
If existing overlay characterization methods are used, then general overlay measurement is possible, but the ability to extract process-induced fingerprints deteriorates
Solution Approach 1:
The patent applies local quality by designing metrology mark structures with specific pattern densities and geometries tailored to each process type. The mark structures have locally optimized characteristics (e.g., different pattern densities for etching vs. CMP) that make them sensitive to specific process-induced overlay errors, enabling selective fingerprint extraction
3Manufacturing precision
If traditional measurement approaches are used, then measurement simplicity is maintained, but the ability to correct nanometer-scale errors deteriorates
Solution Approach 1:
The patent implements preliminary action by measuring and characterizing overlay errors using dedicated metrology mark structures before device fabrication. The system pre-characterizes process-induced fingerprints from patterning, etching, and CMP processes, storing this information for later use in correcting device layer alignment, thereby achieving nanometer-scale precision without adding complexity to the actual device manufacturing
Data Source
AI summary
An apparatus and a method for generating a metrology mark structure that can be formed on a substrate for measuring overlay characteristics induced by one or more processes performed on the substrate by determining features for the metrology mark structure based on a pattern distribution. The method involves obtaining a function to characterize an overlay fingerprint induced by a process performed on a substrate. Based on the function, a pattern distribution is derived, the pattern distribution being indicative of a number of features (e.g., indicative of density) within a portion of the substrate. Based on the pattern distribution, a physical characteristic (e.g., shape, size, etc.) of the features of the metrology mark structure is determined.