Overlay Mark Protection via Dummy Via Density in CMP
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Solution Overview
Problem
The chemical mechanical polishing (CMP) process causes dishing and erosion of overlay marks in semiconductor structures, leading to alignment and measurement accuracy issues, particularly in BEOL and MOL areas, as the number of layers increases, impacting silicon quality and metrology.
Innovation Solution
The method involves forming overlay marks within a layer of a stack and increasing the density of an upper layer by creating vias filled with material, which are then polished to protect the marks from CMP dishing, using dummy features to normalize edge saw line erosion and enhance contrast.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to polish layers, then planarity and surface quality are improved, but overlay marks suffer from dishing and erosion leading to measurement accuracy degradation
Solution Approach 1:
The method performs preliminary action by forming dummy features (via holes filled with material) in the layer containing overlay marks before the CMP process. These dummy features are strategically positioned around the overlay marks to create a protective effect during subsequent polishing, preventing the dishing and erosion that would otherwise damage the marks and compromise measurement accuracy.
Solution Approach 2:
The dummy features are locally concentrated around the overlay marks rather than being uniformly distributed throughout the entire layer. This localized approach creates targeted protection zones where the density increase is most needed to prevent CMP damage to the critical overlay marks, while minimizing unnecessary material addition in other areas.
2Device complexity
If multiple layers are accumulated to shrink design parameters, then device complexity and functionality are improved, but CMP dishing becomes more accentuated affecting overlay mark integrity
Solution Approach 1:
As each new layer is formed in the multi-layer stack, the method performs preliminary action by immediately forming dummy features in that layer around the overlay marks before subsequent CMP processes. This ensures that each layer, regardless of its position in the stack, has protective dummy features in place to prevent dishing accumulation, maintaining overlay mark integrity even as device complexity increases with more layers.
Solution Approach 2:
The dummy features act as a beforehand cushioning mechanism against the cumulative dishing effects of multiple CMP processes. By placing these protective features in advance in each layer, the method creates a buffer that absorbs the progressive damage that would otherwise accumulate as more layers are added to the device structure.
3Reliability
If dummy features are added to increase layer density and protect marks, then overlay mark protection is improved, but device area and manufacturing complexity increase
Solution Approach 1:
The dummy features are strategically positioned only in the immediate vicinity of overlay marks where protection is critical, rather than being uniformly distributed across the entire device area. This localized approach minimizes the total area occupied by dummy features while still providing effective protection to all overlay marks, thus reducing the impact on overall device area.
Solution Approach 2:
The method uses a partial approach by forming dummy features only in specific strategic locations around overlay marks rather than filling the entire layer. This partial action provides sufficient protection for the critical overlay marks without the excessive material addition and area occupation that would result from complete layer filling, achieving an optimal balance between protection and area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the integrity of overlay marks, prevents damage from CMP processes, and enhances measurement accuracy by providing uniform density and increased metal height, allowing for better alignment and verification across multiple layers.
Implementation Method 1
challenges can arise from the patterning of the layers including, more specifically, dishing from a chemical mechanical polishing (CMP) process
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.