Overlay Mark Layout for Dense Electron Beam Overlay Metrology

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Solution Overview

Problem

Current overlay measurement techniques in semiconductor manufacturing are inadequate for complex devices, as they rely on conventional target designs that do not efficiently utilize wafer space and measurement time, leading to suboptimal accuracy and increased production costs.

Innovation Solution

The development of advanced target designs combining electron beam overlay (eOVL) with scatterometry overlay (SCOL) and optical image-based overlay (IBO) targets, which include rotational symmetry and nested polygonal shapes, allowing for denser sampling and increased information content within a smaller area, thereby improving measurement accuracy and reducing measurement time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional overlay measurement targets are used, then the measurement process is simple, but the measurement accuracy and information content are insufficient for complex semiconductor devices

Engineering Contradiction:
Improveoverlay measurement accuracyVSAvoidtarget design complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements nested polygonal shapes (e.g., inner square within outer square, or concentric polygons) within the overlay target structure. This nesting allows multiple measurement features to be contained within a compact area, increasing the information content and measurement accuracy without proportionally increasing the target area. The nested structures provide multiple reference points and measurement zones that can be analyzed simultaneously.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from conventional two-dimensional target designs to three-dimensional structured targets with rotational symmetry and nested polygons. This dimensional enhancement creates multiple measurement planes and reference levels, allowing for more comprehensive overlay analysis. The 3D structure provides additional geometric constraints and reference points that improve measurement precision through multi-dimensional data collection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If more overlay targets are placed on the wafer to increase sampling density, then the measurement accuracy improves, but the wafer real estate increases

Engineering Contradiction:
Improveoverlay measurement accuracyVSAvoidwafer area occupied by targets
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

By nesting multiple measurement features and polygonal structures within a single compact target area, the patent achieves high information content and effective sampling density without increasing the physical wafer area occupied. The nested design allows multiple measurement functions to coexist in a space-efficient manner.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent combines multiple overlay measurement targets and features into a single integrated target structure with rotational symmetry and nested polygons. This merging consolidates what would traditionally require multiple separate targets into one compact unit, maintaining high measurement capability while reducing the total wafer real estate required.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If conventional single-set scanner corrections are applied to all wafers in a lot, then the process is efficient, but the overlay errors cannot be optimized for individual wafer variations

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidoverlay alignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the overlay measurement and correction process by enabling individual measurement of each wafer through enhanced target designs. The segmented target structures allow for wafer-specific overlay error characterization, which can then feed into customized scanner corrections for each wafer, moving away from blanket single-set corrections applied to entire lots.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables dynamic adjustment of overlay correction parameters based on individual wafer measurements. The enhanced target designs provide sufficient measurement data to determine wafer-specific correction parameters, allowing the system to change correction parameters adaptively for each wafer rather than using fixed lot-level corrections.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11862524B2Overlay mark design for electron beam overlay
Publication Date: 2024.01.02 KLA CORP
  • US11862524B2 patent drawing
  • US11862524B2 patent drawing
  • US11862524B2 patent drawing

AI summary

The present disclosure provides a target and a method of performing overlay measurements on a target. The target includes an array of cells comprising a first cell, a second cell, a third cell, and a fourth cell. Each cell includes a periodic structure with a pitch. The periodic structure includes a first section and a second section, separated by a first gap. The target further includes an electron beam overlay target, such that electron beam overlay measurements, advanced imaging metrology, and/or scatterometry measurements can be performed on the target.