Overlay Mark Design for Semiconductor Etching Reliability

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Solution Overview

Problem

The existing overlay marks in semiconductor manufacturing face challenges in accurately measuring overlay accuracy due to etching failures and polymer accumulation during the photolithography process, which obstructs the formation and identification of the overlay mark, thereby reducing the reliability of overlay accuracy measurements.

Innovation Solution

An overlay mark design featuring a main overlay pattern with an opening exposing the substrate and an auxiliary overlay pattern spaced apart from the sidewall, where the auxiliary pattern is used to accumulate byproducts generated during the etching process, reducing etching failures and improving measurement clarity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the second photoresist patterns are arranged more sparsely and made wider in the scribe lane region to form the overlay mark, then the overlay mark can be formed, but polymer accumulates on the exposed portion of the layer during etching, causing etching failures and reducing measurement reliability

Engineering Contradiction:

Improveoverlay mark formationVSAvoidetching process reliability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The photoresist pattern is divided into two distinct regions: a first region with densely arranged narrow patterns for circuit formation, and a second region with sparsely arranged wide patterns for overlay mark formation. This segmentation allows each region to be optimized independently, with the wide second region specifically designed to prevent polymer accumulation during etching while maintaining overlay measurement functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the photoresist pattern are given different local properties: the first region has narrow, densely spaced patterns suitable for high-density circuit fabrication, while the second region has wide, sparsely spaced patterns that prevent polymer accumulation during etching. This local quality differentiation resolves the contradiction by allowing the overlay mark region to have properties optimized for etching reliability without compromising circuit region performance.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If the etching conditions are determined according to the width of the first photoresist pattern in the cell region, then circuit patterns can be formed accurately, but the opening formed using the second photoresist pattern is too wide, causing polymer accumulation and etching stop

Engineering Contradiction:

Improvecircuit pattern formationVSAvoidpolymer accumulation

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The photoresist pattern is segmented into a first region for circuit formation and a second region for overlay marking. The second region is specifically designed with wider, sparser patterns that generate fewer byproducts during etching, thereby preventing polymer accumulation and etching stop while the first region maintains conditions optimized for precise circuit pattern formation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different etching conditions are applied locally to different regions: the first region uses etching conditions optimized for narrow circuit patterns, while the second region uses wider pattern geometry that inherently reduces polymer accumulation. This local quality approach allows each region to operate under optimal conditions without interfering with the other.

Inventive Principle:

Principle #3Local quality

3Reliability

If the overlay mark is formed with wider photoresist patterns to prevent etching failures, then etching reliability improves, but the pattern becomes more difficult to identify for overlay accuracy measurement

Engineering Contradiction:

Improveetching process reliabilityVSAvoidoverlay accuracy measurement

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The photoresist pattern is segmented into a first region with narrow patterns for circuits and a second region with wide patterns for overlay marking. The second region's wider, sparser patterns improve etching reliability by reducing polymer accumulation, while the segmented structure ensures that the overlay mark remains distinct and identifiable for measurement purposes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second region is given local quality characteristics (wider, sparser patterns) that optimize etching reliability, while the overall segmented structure maintains measurement functionality. This local differentiation allows the overlay mark to be both etching-resistant and measurement-visible.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS7736844B2Overlay mark and method of forming the same

Publication Date: 2010.06.15 SAMSUNG ELECTRONICS CO LTD

AI summary

An overlay mark may include a main overlay pattern and an auxiliary overlay pattern, wherein the main overlay pattern may have an opening exposing a substrate and the auxiliary overlay pattern may be formed in the opening. The auxiliary overlay pattern may be spaced apart from a sidewall of the main overlay pattern defining the opening. The thickness ratio of the auxiliary overlay pattern to the main overlay pattern may be about 0.05:1 to about 0.30:1. Accordingly, overlay accuracy measurements may be improved using the clearer overlay mark according to example embodiments.