Overlay Metrology Mark Layout for Sub-20 nm Layer Alignment
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Solution Overview
Problem
Existing overlay marks are inadequate for accurately aligning small-dimension semiconductor layers, leading to potential device performance issues or failure due to improper alignment.
Innovation Solution
An overlay metrology mark with a first and second axis, a target feature at their intersection, and paired alignment features on each axis, designed to determine overlay errors between successive layers, allowing for precise alignment and measurement of relative positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing overlay marks are used for alignment, then the alignment process can be performed, but the measurement precision is insufficient for small-dimension devices below 20 nanometers
Solution Approach 1:
The overlay mark is segmented into distinct functional components: a target feature on the first layer and multiple alignment features on the second layer, arranged along orthogonal axes. This segmentation allows independent optimization of each component's function - the target feature provides a precise reference point while alignment features provide multiple measurement positions, thereby improving measurement precision without compromising manufacturing precision
Solution Approach 2:
The patent introduces an intermediary measurement system that uses the structured overlay mark to mediate between the two successive layers. The overlay mark serves as an intermediary reference structure that can be measured with high precision by overlay measurement tools, enabling accurate determination of relative positions between layers without directly measuring the small-dimension features themselves
2Reliability
If overlay measurement is performed to ensure alignment accuracy, then device performance can be maintained, but the measurement and correction process becomes more complex
Solution Approach 1:
The overlay mark structure is designed with multi-functionality to reduce overall system complexity. The same overlay mark structure serves multiple purposes: providing alignment references along both x and y axes, enabling measurement at multiple positions, and maintaining reliability across different measurement conditions. This universal structure eliminates the need for separate measurement systems for different axes or positions
Solution Approach 2:
The overlay mark is formed as part of the preliminary fabrication steps before final device assembly. By pre-establishing the alignment reference structure during the layer formation process, the patent enables subsequent rapid measurement and correction without adding complex post-fabrication alignment systems, thereby maintaining device reliability while controlling overall complexity
Data Source
AI summary
The present application provides an overlay metrology mark and a method of determining an overlay error during a semiconductor fabrication. The overlay metrology mark, for determining an overlay error between two successive layers of a substrate, includes a first axis, a second axis, a target feature, a first alignment feature, and a second alignment feature. The second axis crosses the first axis. The target feature is disposed at an intersection of the first axis and the second axis. The first alignment feature is arranged on the first axis, the second alignment feature is arranged on the second axis, and the first and second alignment features are in pairs.