Overlay Mark Structure for Precise M0-C0 Alignment Measurement
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Solution Overview
Problem
Existing semiconductor devices face challenges in accurately measuring overlay errors between current and pre-layers due to systematic errors, particularly in lithography operations, which affect the precision of pattern alignment.
Innovation Solution
A semiconductor device with a novel overlay mark structure is introduced, comprising metallization layers as pre-layers and openings defined by a dielectric layer as current layers, allowing for precise alignment measurement without systematic errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional overlay mark structures are used for measuring overlay errors, then measurement can be performed, but systematic errors occur between current layer and pre-layer that reduce measurement precision
Solution Approach 1:
The patent inverts the conventional overlay mark structure by making the current layer (second pattern) larger than the pre-layer (first pattern). This inversion allows the measurement beam to first interact with the larger current layer features and then the smaller pre-layer features, eliminating systematic errors caused by the conventional approach where the measurement beam interacts with pre-layer features first. This principle directly resolves the technical contradiction by improving measurement precision while eliminating systematic errors that compromised reliability.
Solution Approach 2:
The patent introduces dimensional asymmetry between the current layer and pre-layer patterns, creating a size difference that adds a new dimension to the overlay measurement approach. The current layer features are deliberately made larger in dimension than the pre-layer features, creating a dimensional hierarchy that enables more accurate measurement by providing distinct reference points for the measurement beam, thereby improving precision without introducing systematic errors.
2Manufacturing precision
If the second pattern continuously extends across the first pattern segments, then overlay error can be defined along a specific direction, but the structure complexity increases
Solution Approach 1:
The patent segments the first pattern (pre-layer) into multiple separate segments along the first direction, while the second pattern (current layer) continuously extends across these segments. This segmentation creates distinct reference points for precise overlay measurement in the first direction, while the continuous extension of the second pattern provides a unified reference for measurement in the second direction. The segmentation principle enables precise alignment measurement without requiring the entire structure to be complex, as each segment serves a specific measurement function.
Data Source
AI summary
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first pattern and a second pattern. The first pattern is disposed on the substrate. The first pattern includes a first segment and a second segment, each of which extends along a first direction. The second pattern is disposed on the first pattern. The second pattern includes a first part extending along a second direction different from the first direction. The first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. The first pattern and the second pattern are associated with an overlay error.