Overlay Mark Buffer Trenches for Stress Relief
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Solution Overview
Problem
Conventional overlay mark designs in semiconductor manufacturing lead to asymmetric overlay shifts due to film stress, causing misalignment and reliability issues in integrated circuits, particularly at the wafer edge.
Innovation Solution
The introduction of buffer trenches around the scribe line area to release metal film stress, improving the asymmetric overlay mark profile and reducing overlay shifts by using multiple trenches to indicate the position of both lower and upper layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional overlay mark design is used, then overlay measurement can be performed, but asymmetric overlay shift occurs due to film stress
Solution Approach 1:
The patent introduces buffer trenches as an intermediary structure between the overlay marks and the scribe line. These trenches serve as a stress relief mechanism that mediates the conflict between performing overlay measurements and maintaining overlay alignment precision. The buffer trenches absorb metal film stress that would otherwise cause asymmetric overlay shifts, thereby protecting the measurement marks from stress-induced distortion while still allowing measurement functionality.
Solution Approach 2:
The patent segments the scribe line area by introducing buffer trenches that divide the continuous metal film into separate regions. This segmentation prevents stress accumulation across the entire scribe line area and isolates the overlay marks from the stress-generating metal deposition process. The segmented structure allows the overlay marks to maintain their geometric integrity while still enabling measurement functionality.
2Ease of manufacture
If metal film is deposited over overlay marks, then interconnect structure is formed, but film stress causes asymmetric overlay mark profile
Solution Approach 1:
The buffer trenches act as an intermediary structure that allows metal film deposition to proceed for interconnect formation while preventing the stress from distorting the overlay mark profiles. The trenches provide a stress relief zone that decouples the metal deposition process from the overlay mark structure, enabling both interconnect formation and profile integrity.
Solution Approach 2:
The patent extracts the stress-generating metal film from directly over the overlay marks by introducing buffer trenches in the scribe line area. This extraction removes the harmful stress source from the vicinity of the overlay marks while still allowing metal interconnects to be formed in the device area. The overlay marks are thus protected from stress-induced profile distortion.
3Measurement precision
If overlay marks are placed in scribe line area, then alignment measurement is enabled, but metal stress induces overlay shift at wafer edge
Solution Approach 1:
The buffer trenches serve as a stress relief intermediary between the overlay marks and the scribe line structure. They absorb the metal film stress that would otherwise be transmitted to the overlay marks, particularly at the wafer edge where stress accumulation is most severe. This intermediary structure protects the reliability of overlay measurements while maintaining measurement capability.
Solution Approach 2:
The patent applies local quality by introducing buffer trenches specifically in the scribe line area surrounding the overlay marks, while leaving the device area unaffected. This localized modification provides stress relief precisely where needed (at the overlay marks) without interfering with the metal interconnect formation in the device area. The asymmetric overlay shift is thus corrected locally at the mark positions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces metal film-induced stress, mitigates asymmetric overlay mark profiles, and minimizes overlay shifts, enhancing the overall yield and reliability of integrated circuits.
Implementation Method 1
the asymmetric overlay mark profile can be improved by releasing the whole wafer metal stress using the buffer trenches
Data Source
AI summary
An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing means. The first mark is used to indicate the position of a lower layer, the second mark is used to indicate the position of an upper layer; and the stress releasing means is used to release the film stress induced by the upper layer. Unlike the conventional overlay mark arrangements, which will have a severe overlay mark shift due to the film stress, the asymmetric overlay mark profile can be improved by using multiple trenches around the overlay marks according to certain embodiments of the invention disclosed herein.