Integrated Overlay Mark Layout for Accurate Three-Layer Alignment
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Solution Overview
Problem
The existing three-layer overlay method in semiconductor manufacturing requires multiple masks, leading to poor alignment accuracy and excessive structural space occupation, which affects production capacity and product circulation.
Innovation Solution
The method involves creating centrally symmetrical mark groups on multiple material layers, with specific arrangements and orientations to reduce the number of overlay measurements and improve alignment accuracy, including preparing a first mark group on a first material layer, a second mark group on a second material layer, and a third mark group on a third material layer, with centers of symmetry aligned vertically and arranged in perpendicular directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple masks are used for three-layer overlay testing, then overlay measurement can be performed, but alignment accuracy deteriorates and device complexity increases
Solution Approach 1:
The patent combines three separate overlay mark groups (first, second, and third mark groups on different material layers) into a single integrated overlay mark structure. This merging allows the overlay tester to measure all three layers simultaneously using one mask instead of multiple masks, thereby improving alignment accuracy while maintaining comprehensive overlay measurement capability.
2Measurement precision
If multiple masks are used for overlay testing, then comprehensive overlay measurement is achieved, but productivity decreases due to increased measurement time
Solution Approach 1:
The patent merges multiple overlay measurement operations into a single measurement process by integrating three mark groups into one overlay mark. This allows the overlay tester to complete all three overlay measurements (third layer to first layer, third layer to second layer, and second layer to first layer) simultaneously, significantly reducing measurement time and improving production capacity.
Solution Approach 2:
The patent performs preliminary arrangement of the three mark groups in specific spatial relationships (centrally symmetrical patterns with aligned centers of symmetry) before the measurement process. This preliminary configuration enables the overlay tester to acquire all necessary measurement data in a single operation, eliminating the need for sequential measurements and thereby increasing productivity.
3Measurement precision
If multiple test marks are placed in dicing groove, then all overlay measurements can be performed, but area occupied increases excessively
Solution Approach 1:
The patent combines three separate test marks that would traditionally occupy separate positions in the dicing groove into a single integrated overlay mark structure. This merging reduces the number of mask positions required from three to one, thereby conserving valuable dicing groove space and allowing better utilization of the semiconductor wafer area.
Solution Approach 2:
The patent arranges the three mark groups in a vertically stacked configuration along the thickness direction (first, second, and third material layers) rather than spreading them horizontally in the dicing groove. This dimensional reorganization allows all three mark groups to coexist in a compact vertical arrangement, significantly reducing the horizontal space occupied in the dicing groove.
4Measurement precision
If multiple masks are used for three-layer overlay, then measurement coverage is complete, but loss of time increases due to repeated measurements
Solution Approach 1:
The patent merges three separate measurement operations into one simultaneous measurement process by integrating the three mark groups into a single overlay mark. This allows the overlay tester to measure all three layer combinations (1st-3rd layer, 2nd-3rd layer, and 1st-2nd layer) in a single operation, eliminating the time loss associated with performing three separate measurements sequentially.
Data Source
AI summary
The present disclosure discloses an overlay mark, an overlay marking method and an overlay measuring method. The overlay marking method includes at least: preparing a first material layer; preparing a first mark group on the first material layer, and the first mark group is a centrally symmetrical pattern; preparing a second material layer on the first material layer; preparing a second mark group corresponding to the first mark group on the second material layer, and the second mark group is a centrally symmetrical pattern; centers of symmetry of the second mark group and the first mark group are located on the same vertical line; preparing a third material layer on the second material layer; preparing a third mark group corresponding to the first mark group and the second mark group on the third material layer, and the third mark group is a centrally symmetrical pattern.