Overlay Mark Structure for Accurate IC Alignment After Planarization
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Solution Overview
Problem
The planarization process in semiconductor integrated circuit fabrication often causes asymmetrical alignment marks and overlay marks, leading to detection errors and misalignment between semiconductor integrated circuits.
Innovation Solution
Incorporating a semiconductor integrated circuit with an overlay mark structure featuring first and second overlay marks of different widths, allowing for improved alignment accuracy through a measurement and adjustment process before bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a planarization process is performed on semiconductor integrated circuits before bonding, then the surface flatness is improved, but the alignment marks and overlay marks become asymmetrical causing detection errors
Solution Approach 1:
The overlay mark structure is divided into multiple separate overlay marks (first overlay mark, second overlay mark, third overlay mark) with different widths. This segmentation allows the detection system to use different marks for different measurement purposes, compensating for the asymmetry introduced by planarization processing.
Solution Approach 2:
The invention intentionally introduces asymmetry by designing overlay marks with different widths. The first overlay mark has a first width, the second overlay mark has a second width, and the third overlay mark has a third width. This deliberate asymmetry compensates for the unwanted asymmetry caused by planarization, enabling accurate alignment detection.
2Measurement precision
If overlay marks with different widths are used, then alignment accuracy is improved, but the device structure becomes more complex
Solution Approach 1:
The multiple overlay marks with different widths serve universal functions in the alignment process. They can be used together to achieve both rough alignment and precise alignment, as well as to compensate for various types of deformation. This multi-functionality justifies the increased structural complexity by providing comprehensive alignment capabilities.
Data Source
AI summary
A semiconductor integrated circuit, a semiconductor device and a method for aligning semiconductor integrated circuits are provided. The semiconductor integrated circuit includes a substrate and an overlay mark structure in the substrate. The overlay mark structure includes first overlay marks and second overlay marks separated from each other. A first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks.