Overlay Metrology Marks With Non-Uniform Gratings for Wrap-Around Errors
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Solution Overview
Problem
Existing methods for aligning layers in integrated circuits face challenges in accurately determining overlay errors, particularly when the shift in the moire pattern exceeds half of the fringe period, leading to ambiguous results and potential misreporting of overlay errors, known as 'wrap-around error', which can result in incorrect alignment and yield risks.
Innovation Solution
The use of overlay metrology marks with non-uniformly spaced grating lines, forming a moire pattern that allows for unique determination of relative positions even when the shift exceeds half of the fringe period, by creating a moire pattern with varying pitch that distinguishes between small and large changes in position, thereby avoiding wrap-around errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional uniformly spaced grating lines are used for overlay metrology marks, then the manufacturing process is simple, but the measurement precision deteriorates when the shift exceeds half of the fringe period due to wrap-around error
Solution Approach 1:
The patent applies local quality by making the grating line spacing non-uniform across different regions of the overlay metrology mark. Specifically, the grating lines are spaced closer together in some regions and farther apart in others, creating a gradient in spacing. This local variation in spacing allows the moire pattern to provide unambiguous overlay error measurements across the full range of possible shifts, eliminating the wrap-around error that plagues uniform spacing designs while maintaining manufacturing feasibility.
2Reliability
If the dynamic range of overlay measurement is expanded beyond traditional limitations, then the accuracy of overlay error detection is improved, but the complexity of the metrology mark design increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the spacing parameter of the grating lines across the metrology mark. Instead of using a constant spacing, the patent implements a gradient where the spacing between adjacent grating lines changes progressively from one region to another. This parameter variation allows the system to measure overlay errors across a wide dynamic range while maintaining a relatively simple overall structure that can be fabricated using standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of overlay error detection, ensuring precise alignment of layers and reducing the risk of incorrect disposition and yield issues by expanding the effective dynamic range of overlay measurement beyond traditional limitations.
Implementation Method 1
forming a moire pattern that allows for unique determination of relative positions
Data Source
AI summary
Techniques for forming overlay metrology marks are disclosed. In the illustrative embodiment, a first overlay metrology mark is on a first layer of a semiconductor wafer, and a second metrology mark is formed on a second layer above the first layer. The overlay metrology marks are embodied as a series of grating lines. Looking downward at the overlay metrology marks, the two metrology marks form a moire pattern, with the light and dark regions of the moire pattern moving as the relative positions of the overlay metrology marks move. In the illustrative embodiment, at least one of the overlay metrology marks has non-uniform grating line spacing. As a result, the moire pattern is not identical if the overlay metrology mark is shifted by one grating line, allowing for a wider range of overlay errors to be detected.