Overlay Word Line Memory Verification for Secure Cell Operations
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Solution Overview
Problem
Existing memory circuits face challenges in securely verifying that erase, write, and read operations are performed on the intended memory cells, especially when an attacker can manipulate these operations and the verification process.
Innovation Solution
The memory circuit incorporates a design with overlay word lines that allow simultaneous reading and writing operations across multiple word lines, performing logic operations on data words and overlay words to verify the correctness of operations and enhance security through constrained random values and multiple overlay word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address dependent data encryption is used to verify memory operations, then security against attackers is improved, but not all relevant cases are covered and verification reliability is insufficient
Solution Approach 1:
The memory array is divided into multiple independently addressable blocks, each with its own verification capability. This segmentation allows comprehensive coverage of all memory regions while maintaining individual verification reliability, addressing the limitation of previous single-verification approaches that couldn't cover all cases.
Solution Approach 2:
The verification mechanism incorporates feedback loops where read operations are continuously monitored and compared against expected values. This feedback system enables real-time detection of manipulation attempts and ensures that verification reliability is maintained across all memory operations, not just selected cases.
2Reliability
If physical access to the chip is assumed to be possible for attackers, then security requirements are improved, but verification of intended memory cell operations becomes more difficult
Solution Approach 1:
The system preemptively counters potential attacks by implementing verification mechanisms that detect manipulation before it can succeed. By assuming physical access is possible and building defenses against it in advance, the system makes verification of intended operations feasible even under attack conditions.
Solution Approach 2:
An intermediary verification layer is introduced between the attacker and the memory cells. This intermediary mechanism monitors and validates all operations, making it difficult for attackers to manipulate operations on intended memory cells without detection, thus solving the verification difficulty under physical access conditions.
3Productivity
If simultaneous reading from multiple word lines is performed, then productivity is improved, but device complexity increases due to overlay word line structure
Solution Approach 1:
Multiple read operations on different word lines are merged into a single simultaneous operation. The overlay word line structure allows parallel access to multiple memory blocks, achieving high productivity by combining what would traditionally require sequential access into one unified operation.
Solution Approach 2:
The overlay word line structure serves multiple functions simultaneously: it enables parallel reading from multiple word lines, provides verification capabilities, and maintains addressability for individual blocks. This multi-functionality achieves high productivity without proportionally increasing complexity, as the same structural elements serve multiple purposes.
Data Source
AI summary
A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.