Overlay Memory Cell Verification for Secure Read and Write Integrity
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Solution Overview
Problem
Existing memory circuits face challenges in securely verifying that erase, write, and read operations are performed on the intended memory cells, especially when an attacker can manipulate these operations and the verification process.
Innovation Solution
The memory circuit incorporates a design with overlay word lines that allow for simultaneous reading and writing operations across multiple word lines, performing logic operations on data words and overlay words to verify the correctness of operations and ensure data integrity, using constrained random values and multiple overlay word lines for enhanced security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address dependent data encryption is used to verify memory operations, then security against attackers is improved, but not all relevant cases are covered and verification completeness deteriorates
Solution Approach 1:
The memory array is divided into two separate arrays: a first memory array storing data words and a second memory array storing overlay words. This segmentation allows independent verification of data integrity through overlay operations, addressing the limitation of address-dependent encryption by providing structural separation that enables comprehensive verification coverage.
Solution Approach 2:
The patent introduces a temporal dimension to verification by performing sequential overlay operations. Data words are read from the first memory array, overlayed with words from the second memory array in multiple steps, and verified against expected results. This multi-step temporal process ensures complete verification coverage that static address-dependent encryption cannot provide.
2Reliability
If overlay word lines are added to enable simultaneous reading and verification, then security and verification capability are improved, but device complexity increases
Solution Approach 1:
The second memory array serving as overlay storage is designed to be fully integrated with the memory circuit's existing read and write infrastructure. The same word lines, bit lines, and control logic are used for both data storage and overlay operations, allowing the overlay functionality to serve multiple purposes: verification, encryption, and data protection, thereby minimizing additional complexity.
Solution Approach 2:
The patent merges the verification function with the existing memory read operation. Instead of adding separate verification circuitry, the overlay words are read through the same memory interface as data words, and the verification logic is integrated into the memory control unit. This consolidation achieves comprehensive verification while avoiding proportional increases in device complexity.
3Reliability
If multiple overlay word lines are used for enhanced security verification, then security assurance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses the second memory array as a copy/overlay of verification data that can be independently programmed and configured. This copied structure allows flexible deployment of verification patterns without requiring complex hardwired logic, enabling manufacturers to program verification sequences directly into the overlay array, thereby simplifying the manufacturing process while maintaining high security assurance.
Data Source
AI summary
A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.