Overlay Test Pattern Cells for E-Beam IC Alignment Metrology
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Solution Overview
Problem
Inaccurate overlay among different layers of semiconductor devices during the scaling down process leads to high defect rates and inferior quality in integrated circuits, as existing techniques like Box-in-Box or micro-diffraction-based-overlay are not optimal due to their reliance on visible light, which limits their precision and effectiveness.
Innovation Solution
The implementation of overlay test pattern cells in the circuit layout, which are inserted into gaps among functional cell blocks or as replacements for standard filler cells, allowing for accurate overlay measurement using electron beam inspection, enabling more precise and efficient overlay data collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Box-in-Box or micro-diffraction-based-overlay techniques are used, then overlay measurement can be performed using visible light, but the pattern dimensions become larger than state-of-the-art functional circuit blocks, reducing the number and locational distribution of patterns on the wafer
Solution Approach 1:
The patent changes the fundamental parameter of measurement wavelength from visible light to electron beam, enabling overlay pattern dimensions to be reduced to sub-10nm scale while maintaining measurement capability. This parameter change resolves the contradiction by allowing precise overlay measurement without requiring large pattern dimensions that would consume valuable wafer real estate.
2Measurement precision
If overlay test patterns are inserted into gaps among functional cell blocks, then accurate overlay measurement is enabled, but chip utilization is reduced
Solution Approach 1:
The patent merges overlay test pattern cells with standard filler cells, allowing the same structural element to serve dual purposes: maintaining chip layout integrity and enabling overlay measurement. This merging eliminates the need for separate dedicated test pattern areas, thus resolving the contradiction between measurement accuracy and chip utilization by making the measurement function integrated into existing chip structures.
3Loss of information
If more overlay patterns are placed on the wafer to improve measurement coverage, then overlay data completeness increases, but precious wafer real estate is consumed
Solution Approach 1:
By changing the measurement wavelength parameter to electron beam, the patent enables dramatically smaller pattern dimensions (sub-10nm vs. visible light wavelengths), allowing significantly more overlay patterns to be placed on the wafer without consuming excessive real estate. This resolves the contradiction by enabling high data completeness through increased pattern density while minimizing area consumption through reduced individual pattern size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides more accurate and high-throughput overlay measurement results, improving the quality of semiconductor devices by enhancing measurement accuracy and data output without additional chip utilization costs, and allowing for inline measurement during production.
Implementation Method 1
allowing for accurate overlay measurement using electron beam inspection
Data Source
AI summary
Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.