Semiconductor Overlay Pattern Fences for CMP Flatness
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Solution Overview
Problem
As the number of stacked material layers in semiconductor devices increases, an upper-level difference can occur between the overlay pattern and its surrounding areas, leading to defects in subsequent manufacturing processes due to the high integration of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a substrate with a cell region and scribe lane, featuring a first and second overlay pattern structure, outer fences, and inner fences that penetrate insulating layers, which help prevent upper-level differences and reduce defects by functioning as dummy patterns during the CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked material layers is increased to achieve high integration, then device functionality is improved, but upper-level difference between overlay pattern and surrounding areas occurs causing defects
Solution Approach 1:
The patent applies preliminary action by forming a dummy pattern in the overlay pattern region before the main manufacturing process. This dummy pattern compensates for the upper-level difference that would otherwise occur during subsequent lithography processes, preventing focusing failures and overlay defects in advance.
Solution Approach 2:
The patent applies local quality by creating a specific dummy pattern structure (including first and second dummy patterns with different heights) only in the overlay pattern region, while leaving other regions unchanged. This localized approach addresses the upper-level difference problem specifically where it occurs without affecting other areas of the semiconductor device.
2Measurement precision
If overlay pattern is used for alignment, then lithography accuracy is improved, but upper-level difference causes focusing failure in subsequent processes
Solution Approach 1:
The dummy pattern is formed in advance in the overlay pattern region to compensate for upper-level differences before lithography processes are performed. This preliminary compensation ensures that both alignment accuracy and focusing reliability are maintained throughout subsequent manufacturing steps.
Solution Approach 2:
The dummy pattern acts as an intermediary structure that mediates between the overlay pattern and the surrounding areas. By providing a compensating structure with specific height characteristics, it eliminates the upper-level difference that would otherwise cause focusing failure, allowing the overlay pattern to function properly for alignment purposes.
Data Source
AI summary
A semiconductor device includes a substrate including a cell region and a scribe lane surrounding the cell region, a first overlay pattern structure, which is on the scribe lane and includes first sub-patterns extending in a first direction parallel to an upper surface of the substrate, second sub-patterns extending in a second direction parallel to the upper surface of the substrate, a first outer fence surrounding the first sub-patterns and the second sub-patterns in a plan view and defining a first overlay pattern region, and a first inner fence in the first overlay pattern region and between the first sub-patterns and the second sub-patterns, and a lower structure in the cell region and on the scribe lane and between the first sub-patterns, the second sub-patterns, the first outer fence, and the first inner fence.