Overlay Sampling Methodology for Semiconductor Wafer Alignment
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Solution Overview
Problem
Current overlay control methods in semiconductor manufacturing face challenges in efficiently aligning patterned layers on silicon wafers, leading to misalignment issues that can result in short circuits and connection failures, impacting fab yield and profit margins.
Innovation Solution
The proposed solution involves strategically measuring a reduced number of overlay conditions in central fields and a higher number in outer fields on the wafer, using a grid-like pattern of alignment marks to quantify misalignment and improve alignment accuracy while increasing wafer throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If overlay control measures are performed on all fields across the entire wafer surface, then alignment accuracy is improved, but processing time increases and wafer throughput decreases
Solution Approach 1:
The wafer surface is divided into multiple discrete fields, and overlay control is performed selectively on specific fields rather than uniformly across the entire wafer. This segmentation allows the system to focus measurement resources on critical areas while reducing overall processing time.
Solution Approach 2:
Different regions of the wafer are assigned different levels of overlay control based on their specific requirements. Central fields and outer fields are treated differently, with measurement strategies tailored to local needs, thereby optimizing both accuracy and throughput for each region.
2Productivity
If overlay control measures are reduced to increase wafer throughput, then productivity is improved, but alignment accuracy deteriorates
Solution Approach 1:
The patent applies different overlay control strategies to different regions: central fields use one measurement approach while outer fields use another. This local differentiation maintains alignment accuracy in critical regions while reducing measurements in less critical areas, thereby improving overall throughput without sacrificing necessary precision.
Solution Approach 2:
Instead of performing uniform overlay control across all fields, the system performs partial action by selectively measuring only certain fields. This partial measurement approach is sufficient to maintain overall alignment quality while significantly reducing processing time and increasing throughput.
3Measurement precision
If the number of overlay conditions measured per field is increased, then alignment precision is improved, but measurement time and processing complexity increase
Solution Approach 1:
The patent specifies different numbers of overlay conditions to be measured in central fields versus outer fields. By tailoring the measurement intensity to local requirements, the system achieves sufficient measurement precision where needed while reducing overall measurement time across the entire wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time required for wafer alignment, increases the number of wafers processed per hour, and provides improved wafer topography monitoring, achieving accurate alignment and higher fab efficiency compared to conventional methods.
Implementation Method 1
A light source is arranged to provide light towards an optical axis of the imaging device
Implementation Method 2
An imaging device is arranged to measure a first number of overlay conditions at a corresponding first number of overlay structures within an inner field on the wafer
Data Source
AI summary
One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.