Overlay Test Chip Layout for Early Front-End Defect Detection
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Solution Overview
Problem
The challenge of detecting defects in integrated circuit devices, particularly multi-gate transistors, is exacerbated by the constraints of lithographic processes as feature sizes shrink, leading to delays in identifying defects due to the need for a full stack of metal layers, which can take weeks to fabricate, and existing testing methods like DFT and E-test structures are limited in defect detection resolution and layout fidelity.
Innovation Solution
A quick turn test chip design utilizing metal option plates to create pads and interconnects that form comb or chain structures overlying the wafer, allowing early detection of defects like contact-to-gate shorts by probing at the first metal layer, preserving the original diffusion layout and reducing the time and cost associated with fabricating the full metal stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a full stack of metal layers is fabricated for testing, then defect detection capability is improved, but fabrication time increases significantly
Solution Approach 1:
The patent extracts the essential testing function from the complete metal stack by creating a simplified test chip structure that only requires the first metal layer. This allows defect detection to be performed on a subset of the full structure, eliminating the need to fabricate all subsequent metal layers while maintaining the capability to detect critical defects such as contact-to-gate shorts.
Solution Approach 2:
The testing process is segmented into two distinct phases: (1) early defect detection using the first metal layer on a simplified test chip structure, and (2) subsequent full-stack fabrication only for chips that pass the initial screening. This segmentation allows the majority of chips to be tested quickly without the time penalty of fabricating the complete metal stack.
2Ease of manufacture
If conventional DFT or E-test structures are used, then testing can be performed, but defect detection resolution and layout fidelity are limited
Solution Approach 1:
The patent creates a copy of the actual device layout and interconnect structure in the test chip, using the same diffusion patterns, contact locations, and first metal layer routing. This faithful copying ensures that defects detected in the test chip accurately reflect defects in the production devices, maintaining layout fidelity while enabling early detection before full fabrication.
3Quantity of substance
If feature sizes are reduced to increase device density, then chip capacity increases, but lithographic process constraints worsen
Solution Approach 1:
The patent performs partial fabrication by stopping after the first metal layer instead of completing the full metal stack. This partial action allows the benefits of scaled features to be tested and validated without incurring the complete complexity and cost of fabricating all metal layers, particularly when defects are detected early in the process.
Data Source
AI summary
Design of overlay-based front end defect quick turn test chip is described. In an example, an integrated circuit structure includes a device layer including a vertical stack of horizontal nanowires or a fin, a gate electrode over the vertical stack of horizontal nanowires or the fin, a conductive trench contact adjacent to the gate electrode, and a dielectric sidewall spacer between the gate electrode and the conductive trench contact. The integrated circuit structure also includes a metallization layer immediately above the device layer, the metallization layer including a first test pad and a second test pad.