Self-Aligned Via Structure for Overlay-Tolerant Interconnect Scaling
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Solution Overview
Problem
As critical dimensions shrink, aligning connecting vias with metal lines in multi-layer interconnect structures becomes challenging due to issues like overlay shift and critical dimension enlargement, leading to performance degradation and reliability concerns such as via-to-line breakdown, line-to-line leakage, and time-dependent gate oxide breakdown.
Innovation Solution
A self-aligned via structure is formed through selective deposition methods, where inhibitors are used to selectively deposit dielectric materials, allowing for precise alignment of vias with conductive regions, even in cases of lithography misalignment, by utilizing self-assembled monolayers and controlled etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional damascene processes are used to form interconnect structures, then metal lines and vias can be formed, but alignment between connecting vias and metal lines deteriorates as critical dimensions scale down
Solution Approach 1:
The patent implements self-aligned via formation where the via structure automatically aligns with the metal line through selective deposition and etching processes. The inhibitor pattern serves as a self-aligning guide that ensures the via is formed precisely over the metal line without requiring additional alignment steps, thus maintaining manufacturing precision while enabling continued scaling.
Solution Approach 2:
The patent forms an inhibitor pattern on the metal line surface before depositing the dielectric material. This preliminary action creates a protective mask that defines the via location in advance, ensuring precise alignment is achieved before the actual via etching process begins, thereby resolving the alignment issue as dimensions scale down.
2Productivity
If critical dimensions are reduced to increase device density, then more transistors and interconnects can be packed, but overlay shift and critical dimension enlargement occur leading to reliability degradation
Solution Approach 1:
The self-aligned via structure automatically compensates for overlay shifts that occur during lithography. Because the via is defined by the inhibitor pattern on the metal line itself rather than by separate alignment steps, the via maintains precise registration with the metal line even when overlay errors occur, thereby preserving reliability at reduced critical dimensions.
Solution Approach 2:
The inhibitor pattern is deposited on the metal line surface to create a protective mask that prevents dielectric material deposition directly over the metal line. This preliminary protective action ensures that even if overlay shifts occur during subsequent processing, the via will be formed at the correct location, preventing via-to-line breakdown and maintaining reliability.
3Manufacturing precision
If selective deposition with inhibitors is used to form self-aligned vias, then via alignment with metal lines is improved, but process complexity increases
Solution Approach 1:
The patent combines the via alignment function with the existing metal line formation process by depositing the inhibitor pattern directly on the metal line surface. This merging of functions eliminates the need for separate alignment steps and integrates the self-alignment mechanism into the existing fabrication flow, thereby improving via alignment precision without proportionally increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned via structure enhances reliability, reduces RC performance, and lowers capacitance, providing improved alignment and tolerance to lithography misalignment, thereby increasing the reliability and performance of multi-layer interconnects.
Implementation Method 1
selective deposition methods, where inhibitors are used to selectively deposit dielectric materials
Implementation Method 2
by utilizing self-assembled monolayers and controlled etching processes
Data Source
AI summary
In one embodiment, a self-aligned via is presented. In one embodiment, an inhibitor layer is selectively deposited on the lower conductive region. In one embodiment, a dielectric is selectively deposited on the lower conductive region. In one embodiment, the deposited dielectric may be selectively etched. In one embodiment, an inhibitor is selectively deposited on the lower dielectric region. In one embodiment, a dielectric is selectively deposited on the lower dielectric region. In one embodiment, the deposited dielectric over the lower conductive region has a different etch rate than the deposited dielectric over the lower dielectric region which may lead to a via structure that is aligned with the lower conductive region.