Overlay Vernier Symmetry via Selective Polysilicon Etching
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Solution Overview
Problem
As design rule parameters of semiconductor devices decrease, forming an overlay vernier with clear alignment characteristics becomes increasingly difficult due to reduced step differences and unsymmetrical edges, leading to degraded overlay characteristics and reduced yield.
Innovation Solution
A method involving etching a semiconductor substrate to form recess and overlay vernier regions, followed by forming a gate oxide film and polysilicon layer, planarizing, and using a dry etching process with a key open mask to maintain and enhance the step difference of the overlay vernier region, ensuring symmetry and clarity for alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rule parameters are decreased to improve device integration, then manufacturing complexity increases, but overlay vernier alignment characteristics are degraded due to reduced step difference and unsymmetrical edges
Solution Approach 1:
The gate polysilicon layer formation process is segmented into two distinct stages: first filling the recess gate region, then selectively removing polysilicon from the overlay vernier region. This segmentation allows the overlay vernier to maintain its structural integrity and symmetrical edges while the recess gate receives the necessary polysilicon fill, resolving the conflict between device integration and alignment characteristics
Solution Approach 2:
The gate polysilicon layer is extracted (removed) from the overlay vernier region after initial formation. By using a key open mask to selectively remove polysilicon only from the overlay vernier area, the invention preserves the deep step difference and symmetrical edges necessary for precise alignment, while maintaining polysilicon in the recess gate region for device functionality
2Ease of manufacture
If the gate polysilicon layer is formed to fill the recess gate region, then the recess gate is properly formed, but the overlay vernier step difference becomes less prominent and edges become unsymmetrical
Solution Approach 1:
Different regions of the gate polysilicon layer are given different qualities: the recess gate region retains polysilicon for proper gate formation, while the overlay vernier region has polysilicon removed to maintain deep step difference and symmetrical edges. The key open mask enables this local differentiation, allowing each region to have the polysilicon presence or absence that best serves its specific function
Solution Approach 2:
The overlay vernier region is prepared in advance by forming the gate polysilicon layer that fills it initially, then a key open mask is applied to selectively remove polysilicon from this region before the final gate formation step. This preliminary removal action ensures that when the gate is formed, the overlay vernier already has the proper deep step difference and symmetrical edges for alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a clear and symmetric overlay vernier, improving alignment reproducibility and yield by maintaining the step difference, thus enhancing the reliability and process yield of semiconductor devices.
Implementation Method 1
Step (d) may include a dry etching process with a key open mask which exposes the overlay vernier region
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a key open mask for coating a cell region in order to a gate polysilicon layer over an overlay vernier region formed in a gate forming process, and removing the gate polysilicon layer of the overlay vernier region while regulating an etching process so that the overlay vernier region has a superior shape.