Overlying Gate Structure for Transistor Contact Alignment
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Solution Overview
Problem
In microelectronics, transistors with relatively wide horizontal dimensions pose challenges due to misalignment between gate contacts and underlying gates, leading to higher gate resistance, as existing technologies struggle to reduce the two-dimensional area and power consumption while maintaining device density.
Innovation Solution
The implementation of an overlying gate structure with a greater horizontal width than the polysilicon gate structure, formed through selective epitaxial growth, which increases the physical interface with the gate contact, reducing misalignment risks and allowing for increased contact area without expanding the transistor's dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the transistor gate horizontal width is increased to improve manufacturing tolerance, then misalignment risk decreases, but the two-dimensional area occupied by the device increases
Solution Approach 1:
The patent extends the gate structure in the vertical dimension by adding an overlying gate layer on top of the polysilicon gate structure. This allows the gate contact to align with the wider overlying gate rather than the narrower polysilicon gate, effectively solving the alignment problem without increasing the horizontal footprint of the device.
Solution Approach 2:
The gate structure is divided into two distinct segments: the polysilicon gate structure that interfaces with the channel region, and the overlying gate that provides the contact interface. This segmentation allows each part to serve its specific function optimally - the polysilicon gate for transistor control and the overlying gate for contact alignment.
2Reliability
If the gate contact area is increased to reduce gate resistance, then contact efficiency improves, but the device dimensions expand
Solution Approach 1:
The contact area is increased by utilizing the vertical dimension - the overlying gate extends the gate structure upward, providing a larger contact surface area without expanding the horizontal dimensions of the device. This allows for reduced gate resistance while maintaining compact device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of misalignment and enhances contact efficiency, maintaining high device density while minimizing power consumption and heat generation, thus improving transistor performance and chip efficiency.
Implementation Method 1
formed through selective epitaxial growth
Data Source
AI summary
Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.