Oversampled ADC Time Delay for Precise Fractional Phase Control
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Solution Overview
Problem
Existing digital sensor systems face challenges in interfacing analog signals with digital electronics, particularly in accurately processing and delaying oversampled signals to maintain phase information and achieve desired dynamic ranges.
Innovation Solution
The implementation of a time delay mechanism within the oversampled domain of digital sensor systems, allowing for integer and fractional delays in analog-to-digital converters (ADCs), which can be programmable and applied at various stages of the signal processing, enables precise control over the timing of digital signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional digital signal processing methods are used to achieve time delay, then the system can process digital signals, but the computational complexity increases significantly and phase information accuracy deteriorates
Solution Approach 1:
The patent replaces traditional digital signal processing methods (computational approach) with a time-domain delay mechanism implemented in the analog-to-digital conversion stage. Instead of using complex algorithms to achieve time delay effects, the system introduces a simple time delay element that operates on the oversampled digital signal, thereby reducing computational complexity while maintaining or improving phase information accuracy.
Solution Approach 2:
The patent changes the operating domain from baseband sampling to oversampled domain, and introduces a time delay parameter that can be adjusted independently of the sampling rate. By operating in the oversampled domain with higher sampling rates, the system achieves finer time resolution for phase information while the time delay parameter provides direct control without requiring complex computational operations.
2Reliability
If oversampling is applied to increase dynamic range, then the dynamic range improves, but the processing complexity and data volume increase
Solution Approach 1:
The patent applies time delay in the oversampled domain before decimation and further processing stages. By performing the time delay operation on the oversampled signal prior to reducing the sampling rate, the system maintains phase information accuracy throughout the processing chain. This preliminary action prevents the need for more complex operations later that would be required to correct phase errors introduced at lower sampling rates.
3Loss of time
If time delay is applied in the baseband domain, then the delay can be implemented, but the delay resolution is limited by the sampling rate
Solution Approach 1:
The patent moves the time delay operation from the baseband sampling domain to the oversampled domain, effectively adding a dimension of temporal resolution. By operating at a higher sampling rate (oversampled domain), the system achieves finer time delay precision because the higher sampling rate provides more discrete time points between signal events, enabling more precise delay control without being constrained by the lower baseband sampling rate.
Data Source
AI summary
Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.