Oversampled ADC Time Delay for Precise Phase Alignment
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Solution Overview
Problem
Interfacing analog signals with digital electronics presents a challenge due to the need for converting continuous analog signals into digital formats, particularly in digitally oversampled sensor systems, where existing methods struggle with effectively applying time delays to maintain signal integrity and phase information.
Innovation Solution
A time delay is introduced in the oversampled domain within the analog-to-digital converter (ADC) system, allowing for both integer and fractional delays to be applied to the digital signal, using programmable delay elements such as buffers or delay lines, which can be adjusted to maintain signal integrity and facilitate processes like beamforming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If time delay is applied in traditionally downsampled domain, then signal processing can be performed, but computational intensity increases and phase information may be lost
Solution Approach 1:
The patent applies time delay in the oversampled domain rather than the downsampled domain, effectively changing the dimensional space where signal processing occurs. This dimensional shift allows for more precise phase control with reduced computational burden, as the higher sampling rate provides finer temporal resolution without requiring intensive post-processing algorithms
2Measurement precision
If integer delay only is applied in oversampled domain, then implementation is simpler, but fractional delay precision is lost
Solution Approach 1:
The time delay is segmented into integer and fractional components, where the integer delay is implemented through simple buffering and the fractional delay is achieved through selective sampling of the oversampled signal. This segmentation allows precise total delay control while maintaining implementation simplicity by handling each component through appropriate methods
Solution Approach 2:
The system applies partial action by using only the necessary fractional samples from the oversampled signal to achieve the required fractional delay, rather than implementing a complete fractional delay algorithm. This approach achieves sufficient precision without the full computational overhead of traditional fractional delay methods
Data Source
AI summary
Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.