2× Oversampled Channelizer Reconfiguration Without Duplicative Circuitry
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Solution Overview
Problem
Existing channelizer architectures are inefficient due to duplicative circuitry, over-reliance on large registers, and underutilized mathematical operators, making them unsuitable for applications requiring dynamic reconfiguration and flexibility in size and power-constrained environments such as airborne or spaceborne platforms.
Innovation Solution
A dynamically reconfigurable 2× oversampled channelizer using pipelined stages, polyphase filters, two-phase reorder circuits, FFT circuits, and two-phase merge circuits, allowing for dynamic adjustment of filter coefficients, number of frequency bins, and filter folds, optimized for implementation in FPGAs and ASICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing channelizer architectures are used, then channelization function is provided, but resource duplication and inefficiency occur leading to increased device complexity and power consumption
Solution Approach 1:
The patent merges multiple channelizer functions into a single reconfigurable architecture that can dynamically adjust to different channelization requirements. Instead of having separate dedicated circuitry for each channelization configuration, the system combines multiple functions into one unified structure that can be reconfigured via software control, thereby eliminating resource duplication and reducing overall device complexity.
Solution Approach 2:
The patent implements dynamic reconfiguration capability that allows the channelizer to adapt its structure and parameters in real-time based on operational requirements. The system can dynamically change filter coefficients, number of frequency bins, and other parameters without requiring physical hardware changes, enabling efficient resource utilization across different operating conditions and reducing the need for duplicative circuitry.
2Adaptability or versatility
If existing channelizer architectures are used, then channelization is performed, but large registers are over-relied upon increasing device complexity and reducing flexibility
Solution Approach 1:
The patent employs parameter changes to achieve reconfiguration flexibility without relying on large registers. By dynamically adjusting operational parameters such as filter coefficients, sampling rates, and frequency bin configurations through software control, the system achieves adaptability while minimizing the need for extensive hardware register resources, thereby reducing device complexity.
3Productivity
If existing channelizer architectures are used, then basic channelization is achieved, but mathematical operators are underutilized reducing productivity
Solution Approach 1:
The patent ensures continuous utilization of mathematical operators by designing the channelizer to maintain active processing across all operational modes. The reconfigurable architecture keeps computational resources continuously engaged by dynamically adjusting operations rather than leaving them idle or underutilized, thereby improving productivity while maintaining efficient circuitry usage through sustained meaningful computation.
Data Source
AI summary
Techniques are provided for a dynamically reconfigurable two times (2×) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2× oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2× oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.