Oversampled Unit Interval Mapping for Jitter-Tolerant Receivers
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Solution Overview
Problem
Existing phase tracking techniques in high-speed serial data receivers face limitations due to loop latency and assumptions about consistent oversampled data (OSD) groups, which are not valid during fast and large jitter conditions, leading to poor performance with DVI non-compliant transmitters and increased electromagnetic interference.
Innovation Solution
A chip with sampling circuitry and logic that produces oversampled data and determines which data points belong to different unit intervals, allowing for flexible handling of varying OSD group sizes through a pipelined structure that evaluates sections of data concurrently and adapts to changing jitter conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional phase tracking techniques are used with fixed assumptions about oversampled data groups, then the system is simple to implement, but the system cannot adapt to fast and large jitter conditions
Solution Approach 1:
The patent implements dynamic determination of unit interval boundaries by allowing the number of oversampled data points per unit interval to vary based on actual signal conditions. Instead of fixed assumptions, the system dynamically adjusts the grouping of oversampled data according to detected edge positions and timing information, enabling adaptation to fast and large jitter while maintaining reasonable complexity through systematic evaluation logic.
Solution Approach 2:
The system changes the parameter of unit interval structure from fixed to variable by allowing different numbers of oversampled data points in different unit intervals. This parameter change enables the system to adapt to varying jitter conditions, where some unit intervals may contain fewer or more oversampled points than the typical assumption, directly improving adaptability to non-compliant transmitters and jittery signals.
2Speed
If loop latency is reduced to respond faster to jitter, then the response speed improves, but the reliability of phase tracking decreases
Solution Approach 1:
The patent applies preliminary action by evaluating and determining the correct unit interval boundaries and oversampled data grouping in advance, before actual phase tracking decisions are made. The system proactively identifies timing variations and adjusts its interpretation of oversampled data groups based on predicted unit interval structures, allowing fast response to jitter without sacrificing reliability because the evaluation is performed systematically ahead of time.
3Measurement precision
If the system assumes consistent oversampled data groups, then the processing is straightforward, but the measurement precision of bit values deteriorates under jitter
Solution Approach 1:
The patent segments the evaluation process into distinct stages: first determining unit interval boundaries based on edge detection and timing information, then grouping oversampled data points into unit intervals, and finally determining bit values from each unit interval. This segmentation allows precise bit value determination even under jitter by systematically evaluating each segment separately, while managing complexity through a structured multi-stage approach rather than a monolithic complex algorithm.
Data Source
AI summary
In some embodiments, a chip includes sampling circuitry to produce oversampled data from a received signal, and logic to determine which of the oversampled data are to be part of different unit intervals, wherein some of the unit intervals have a number of oversampled data that is different than a number of oversampled data typically included in the unit intervals. Other embodiments are described and claimed.