Oversampled Read-Channel PLL for Tape Speed Phase Correction
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Solution Overview
Problem
Conventional tape drive storage systems face challenges in maintaining phase alignment during read operations due to variations in tape velocity, which disrupts the phase alignment of read signals.
Innovation Solution
A phase lock loop (PLL) in the read channel uses an oversampled digital signal in the feedback loop to the soft output Viterbi algorithm (SOVA) detector, determining a phase gradient and providing phase corrections to maintain alignment, even with high variations in tape velocity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL is used for phase alignment, then the system structure is simple, but phase alignment is disrupted by tape speed variations
Solution Approach 1:
The patent implements a dynamic phase correction mechanism where the PLL continuously adjusts phase alignment based on real-time tape speed variations. The system uses a phase detector to monitor phase errors and a phase accumulator to dynamically correct these errors, allowing the PLL to adapt to changing tape velocities while maintaining reliable phase alignment across multiple data tracks.
2Reliability
If tape speed control is improved mechanically, then phase alignment may be maintained, but device complexity and cost increase
Solution Approach 1:
The patent replaces complex mechanical speed control systems with a digital signal processing approach. Instead of using mechanical mechanisms to maintain constant tape speed, the invention uses a PLL with phase detection and digital correction algorithms to compensate for speed variations. This substitution of mechanical systems with electronic/digital systems reduces mechanical complexity while achieving the same phase alignment reliability.
3Measurement precision
If oversampled digital signal is used in feedback loop, then phase alignment accuracy is improved, but data processing complexity increases
Solution Approach 1:
The patent changes the sampling parameter by using oversampled digital signals in the PLL feedback loop. Instead of processing signals at the minimum required rate, the system uses higher sampling rates to capture more phase information, improving detection accuracy. The phase detector processes these oversampled signals to extract more precise phase error measurements, enabling better phase alignment while the increased sampling rate provides more data points for accurate phase gradient calculation.
Data Source
AI summary
Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.