Oversampled RF Filtering Circuit for 60 GHz Power Confinement
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Solution Overview
Problem
Existing filtering circuits face challenges in efficiently concentrating the power of radio frequency signals within specific frequency bands, particularly in the 60 GHz band, due to inadequate filtering of secondary lobes, leading to power leakage outside the desired range.
Innovation Solution
A radio frequency transmitter is designed with a filtering circuit comprising a series/parallel shift register and a summing circuit, utilizing coefficients determined by an interpolation filter's impulse response to achieve efficient power concentration within the desired frequency band by oversampling the binary data signal and applying coefficients that recalculate the signal outputs to ensure proper filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional filtering circuits are used to shape radiofrequency signals, then signal transmission occurs, but secondary lobes are inadequately filtered causing power leakage outside the desired frequency band
Solution Approach 1:
The filtering function is segmented into multiple parallel filtering paths, each handling specific frequency components. The shift register outputs are distributed to multiple filtering circuits that process different portions of the signal spectrum simultaneously, improving overall filtering precision and reducing power leakage in secondary lobes.
Solution Approach 2:
The invention transitions from traditional single-path filtering to a multi-dimensional parallel processing architecture. By oversampling the binary data signal and distributing it across multiple parallel filtering circuits, the system adds temporal and spatial dimensions to the filtering process, achieving superior frequency selectivity and reducing power leakage outside the desired band.
2Manufacturing precision
If filtering circuits are designed to concentrate signal power within specific frequency bands, then filtering precision improves, but device complexity and surface area increase
Solution Approach 1:
Multiple filtering circuits are merged into a unified parallel architecture where each circuit processes a portion of the oversampled signal. The outputs of these parallel circuits are combined through summing to produce the final filtered output. This merging approach achieves high filtering precision while distributing complexity across modular units that can be efficiently implemented in integrated circuit form.
Solution Approach 2:
The parallel filtering circuit architecture is designed to be universally applicable across different frequency bands and signal types. The same structural framework can be configured for various radiofrequency applications by adjusting the filtering parameters and coefficients, reducing overall device complexity through reuse of proven design modules.
3Device complexity
If traditional filtering methods are used, then circuit implementation is simpler, but signal power is not adequately concentrated within the desired frequency band
Solution Approach 1:
The binary data signal is oversampled before being distributed to the parallel filtering circuits. This preliminary oversampling action creates multiple temporal copies of each data bit, which are then processed in parallel through the filtering circuits. This preliminary preparation enables the subsequent filtering stage to effectively concentrate signal power within the desired frequency band while maintaining manageable circuit complexity.
Data Source
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AI summary
This description relates to a radio frequency transmitter comprising at least one filtering circuit (400) including: a serial/parallel shift register (402) including a binary input (In) and N binary outputs Oi, with N an integer greater than or equal to OSR, OSR an integer greater than or equal to 2, and i an integer index from 0 to N-1, the register receiving a binary data signal (DATA) at a frequency Fdata on its input (In) and implementing shifts on its outputs Oi at a frequency equal to Fdata*OSR; a circuit (404) defined by N coefficients Ci providing, for each non-zero coefficient Ci, a signal SIGi determined by the coefficient Ci and by the corresponding output Oi; and a summing circuit (408, 502) providing an output (OUT) equal to the sum of the SIGi signals.