Oversampling ADC Clock Phasing for Low-Power Stable Noise Shaping
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Solution Overview
Problem
Existing low power circuit designs for oversampling analog-to-digital converters (ADCs) face challenges in achieving optimal noise transfer function (NTF) stability, leading to increased power consumption and reduced maximum signal levels due to excessive in-band quantization noise and noise gain, which complicates the trade-off between noise reduction and loop stability.
Innovation Solution
The implementation of an optimized loop filter with a de-coupling technique to reduce coupling among integrator stages and the use of uneven non-overlapping clock phases to minimize power consumption, along with a delay lock loop for precise timing control, ensures accurate noise transfer function and reduced power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional loop filter design is used in oversampling ADCs, then in-band quantization noise is reduced, but noise gain increases excessively leading to loop instability and increased power consumption
Solution Approach 1:
A noise gain compensation circuit is introduced as an intermediary element that specifically targets and compensates for the excessive noise gain in the loop filter. This circuit acts as a mediator between the loop filter and quantizer, providing negative feedback to reduce noise gain without affecting the in-band noise shaping performance, thereby resolving the stability issue while maintaining noise reduction
2Object-affected harmful factors
If conventional loop filter design is used in oversampling ADCs, then in-band quantization noise is reduced, but power consumption increases
Solution Approach 1:
The noise gain compensation circuit serves as an intermediary that enables lower power consumption by stabilizing the loop early in the signal path. This prevents excessive signal swing and reduces the power required by subsequent stages, particularly the quantizer and digital filter, while maintaining effective in-band noise shaping
3Object-affected harmful factors
If conventional loop filter design is used in oversampling ADCs, then in-band quantization noise is reduced, but maximum signal level decreases
Solution Approach 1:
The noise gain compensation circuit introduces an intermediary feedback path that specifically counteracts noise gain without attenuating the signal path. This allows the ADC to maintain higher maximum signal levels by preventing noise gain from limiting the signal swing, while preserving the in-band noise shaping characteristics
4Measurement precision
If oversampling ADC architecture is used, then high conversion resolution is achieved with simple quantizer, but complex digital signal processing is required
Solution Approach 1:
The invention extracts and addresses the noise gain issue specifically within the analog loop filter stage, separating this problem from the digital signal processing domain. By compensating for noise gain in the analog domain, the digital filter's workload is reduced, allowing for simpler digital implementation while maintaining high conversion resolution
Data Source
AI summary
Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.