Multi-Channel Oversampling ADC With Noise-Shaping Feedback Loops
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face limitations in achieving high instantaneous bandwidth and resolution, particularly at very high sample rates, due to issues such as quantization noise, clock jitter, and thermal noise, which restrict their performance in modern electronic applications.
Innovation Solution
The proposed solution involves a Multi-Channel Bandpass Oversampling (MBO) converter that employs continuous-time Diplexed Feedback Loops (DFLs) for quantization noise shaping, Moving Average Reconstruction (MAR) filters for signal reconstruction, and active noise-shaping filter calibration, enabling improved performance at high sample rates and bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash converters are used to achieve very high instantaneous bandwidth, then the instantaneous bandwidth can exceed 10 GHz, but the resolution is limited to about 9 bits due to quantization errors from clock jitter, thermal noise, and component tolerances
Solution Approach 1:
The converter is divided into multiple parallel sub-converters (e.g., 4 sub-converters), each processing a portion of the input signal. Each sub-converter operates at the high instantaneous bandwidth required, and their outputs are combined through digital processing to achieve the overall high-resolution conversion, thereby resolving the contradiction between speed and precision
Solution Approach 2:
Multiple high-bandwidth sub-converters are merged in parallel to achieve both the required instantaneous bandwidth and high resolution. The combining process uses digital signal processing to integrate the outputs of individual sub-converters, achieving resolution beyond what a single flash converter could provide while maintaining the high bandwidth capability
2Measurement precision
If conventional pipeline converters are used to achieve better precision with complex calibration schemes, then the conversion resolution can exceed 9 bits, but the instantaneous bandwidth is reduced to less than about 1 GHz
Solution Approach 1:
The conversion process is segmented into multiple parallel paths, each handling a portion of the bandwidth requirement. This allows each segment to operate at higher speeds without the need for complex inter-stage calibration, thereby maintaining both high resolution and high instantaneous bandwidth simultaneously
3Measurement precision
If oversampling converters are used to reduce quantization noise through noise-shaping, then high resolution can be achieved, but the device complexity increases due to delta-sigma modulators and reconstruction filters
Solution Approach 1:
The complex noise-shaping and reconstruction filter functions are extracted from the high-speed conversion path and implemented separately in the digital domain at lower speeds. This allows the analog front-end to remain simple and high-speed, while the resolution enhancement is achieved through digital processing, thereby reducing overall device complexity
Solution Approach 2:
A digital intermediary processing stage is introduced between the high-speed sub-converters and the final output. This intermediary performs the noise-shaping and reconstruction functions in the digital domain, acting as a mediator that achieves high resolution without requiring complex analog circuitry in the high-speed path
Data Source
Figure 1A~2
Figure 1B~1C
Figure 3A~3B
AI summary
Provided are, among other things, systems, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. According to one representative embodiment, an apparatus includes multiple quantization-noise-shaping continuous-time filters, each in a separate processing branch and having an adder that includes multiple inputs and an output; an input signal is coupled to one of the inputs of the adder; the output of the adder is coupled to one of the inputs of the adder through a first filter; and the output of a sampling/quantization circuit in the same processing branch is coupled to one of the inputs of the adder through a second filter, with the second filter having a different transfer function than the first filter.