Oversampling Clock for CAN Receiver Frequency Drift Compensation
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Solution Overview
Problem
Conventional communication receivers require accurate and costly sample clocks with tight frequency tolerance to ensure successful decoding of CAN frames, which is economically challenging due to the need for crystal oscillators or post-fabrication trimming.
Innovation Solution
Implementing an oversampling clock with a frequency N times that of the nominal sampling clock, allowing multiple sampling intervals within each bit interval and using multiple decoders to account for frequency variations, ensuring successful decoding across a range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sample clock with tight frequency tolerance (±2%) is used to ensure successful CAN frame decoding, then decoding reliability is improved, but manufacturing cost increases due to requiring crystal oscillators or post-fabrication trimming
Solution Approach 1:
The patent changes the sampling frequency parameter by using an oversampling clock with frequency N times higher than the nominal sampling clock. This allows the system to tolerate larger frequency deviations (up to ±20%) in the sample clock while maintaining successful frame decoding, thereby eliminating the need for expensive crystal oscillators or post-fabrication trimming operations
Solution Approach 2:
The patent introduces dynamic resampling functionality where the receiver can adjust its sampling timing based on detected frequency variations. The frame processor dynamically determines resampling parameters and resamples the incoming signal at adjusted timing to compensate for clock frequency inaccuracies, enabling reliable decoding without tight clock tolerance
2Ease of manufacture
If the sample clock frequency drifts by ±2% from nominal value, then manufacturing cost is reduced by avoiding crystal oscillators, but frame decoding reliability deteriorates due to temporal misalignment between sampling points and transmitted bits
Solution Approach 1:
The patent implements a feedback mechanism where the frame processor monitors the incoming signal for frequency variations and adjusts the resampling timing accordingly. The system detects timing errors caused by clock drift and dynamically compensates by resampling at adjusted intervals, ensuring reliable decoding even when the sample clock frequency drifts by ±2% or more
Solution Approach 2:
The patent performs preliminary frequency estimation and resampling parameter determination before actual frame decoding. The frame processor pre-calculates the appropriate resampling timing based on detected frequency variations, allowing it to compensate for clock inaccuracies before they cause decoding failures
Data Source
AI summary
The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The compensation employs an oversampling clock whose frequency defines a sampling interval that is smaller than the bit interval, which bit interval is nominally a predetermined integer multiple of the sampling interval. The oversampling clock samples the received transmission to produce an incoming sample stream. The incoming sample stream is decoded by a plurality of different decoding operations to produce, respectively, a plurality of decoded sample streams. It is determined whether the received transmission is decodable from any of the decoded sample streams.