Oversampling PLL Phase Error Detection for Low In-Band Noise
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Solution Overview
Problem
Charge pump phase-locked loops (PLLs) face challenges in integrating with digital baseband signal processing blocks due to analog circuit requirements, leading to limitations in reducing in-band noise and fractional spur noise in RF frequency synthesizers, which affect communication quality.
Innovation Solution
A phase-locked loop circuit utilizing an oversampling scheme to detect phase errors, comprising a voltage-controlled oscillator, divider, phase-frequency error detector, sampler, window phase error detector, residue phase error detector, adder, and loop filter, which generate error compensation signals to improve phase locking and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a charge pump phase-locked loop is used for RF frequency synthesis, then frequency synthesis capability is achieved, but integration with digital baseband signal processing blocks is difficult due to analog circuit requirements
Solution Approach 1:
The patent replaces the traditional analog charge pump mechanism with a digital-based phase error detection system. The phase-frequency error detector and window phase error detector use digital logic to detect phase errors, eliminating the need for analog charge pump circuits and enabling full digital implementation that can be integrated with digital baseband signal processing blocks.
Solution Approach 2:
The patent introduces a sampler as an intermediary component that converts the analog VCO clock signal into a digital sampling clock signal. This sampler acts as a bridge between the analog VCO and the digital phase error detectors, enabling digital processing while maintaining the ability to control the analog VCO through the loop filter.
2Adaptability or versatility
If a digital RF PLL is used to integrate with digital baseband signal processing, then integration is improved, but in-band noise and fractional spur reduction is limited due to digital quantization noise
Solution Approach 1:
The patent segments the phase error detection process into three distinct components: phase-frequency error detection for large phase differences, window phase error detection for medium phase differences, and residue phase error detection for small phase differences. This segmentation allows each detector to be optimized for its specific range, improving overall noise performance while maintaining digital implementation.
Solution Approach 2:
The patent implements dynamic switching between different phase error detection mechanisms based on the magnitude of the phase error. The system automatically selects the appropriate detector (phase-frequency, window, or residue) depending on the current phase error condition, enabling optimal noise performance across all operating conditions while maintaining digital implementation.
3Object-affected harmful factors
If oversampling is used to reduce in-band noise, then in-band noise reduction is achieved, but device complexity increases due to additional detectors and sampling circuitry
Solution Approach 1:
The patent merges the functions of multiple phase error detectors into a unified system where the phase-frequency error detector, window phase error detector, and residue phase error detector work together. The adder combines their outputs to produce a comprehensive phase error compensation signal, achieving noise reduction through coordinated operation rather than requiring separate independent systems.
Solution Approach 2:
The sampler serves multiple functions: it converts the analog VCO clock to a digital sampling clock, provides timing information for the phase error detectors, and enables the oversampling mechanism that reduces in-band noise. This multi-functionality reduces the need for additional dedicated components, mitigating the complexity increase.
Data Source
AI summary
A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.