Oversampling Receiver Circuit for Jitter-Robust eARC Duty Detection
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Solution Overview
Problem
Existing receivers face increased error in determining the duty cycle of audio signals due to jitter, affecting the accuracy of logical value determination for digital output signals in Enhanced Audio Return Channel (eARC) applications.
Innovation Solution
A receiver design incorporating a sampling circuit, data sampling point selection circuit, and determination circuit, which uses a clock signal to oversample the input signal, filters the start point data, and adds an offset to generate a data sampling point, allowing for accurate determination of the logical value of the digital output signal by referencing the sampled value at the data sampling point.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional duty cycle detection method is used, then the receiver can determine logical values from audio signals, but jitter in audio signals increases the error in judging the duty cycle
Solution Approach 1:
The patent applies preliminary action by performing multiple sampling operations before final duty cycle determination. The receiver samples the audio signal multiple times within a sampling window to obtain multiple duty cycle values, then averages these values to determine the final duty cycle. This preliminary sampling and averaging process eliminates the impact of jitter on single-sample accuracy, resolving the contradiction between measurement precision and reliability.
2Measurement precision
If oversampling is implemented to improve duty cycle determination accuracy, then measurement precision increases, but device complexity increases due to additional sampling and processing circuits
Solution Approach 1:
The patent applies universality by designing the sampling circuit to serve multiple functions: it samples the audio signal for duty cycle determination, and the same sampled data is reused for both 40% and 60% duty cycle detection. The determination circuit also performs multiple comparison operations using the same sampled values. This multi-functional approach achieves high measurement precision without proportionally increasing device complexity.
3Measurement precision
If multiple sampling points are used to reduce jitter impact, then duty cycle measurement accuracy improves, but loss of time increases due to extended sampling duration
Solution Approach 1:
The patent applies partial action by sampling the audio signal at multiple points within a limited sampling window rather than continuously over an extended period. The receiver performs 3-7 sampling operations within a single audio signal period, which is sufficient to capture the duty cycle information and average out jitter effects without requiring the full duration of multiple signal periods. This achieves improved measurement precision with minimal time loss.
Data Source
AI summary
The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.